nanamake/r22sdf

Stars
24
Rank 980,943 (Top 20 %)
Language Verilog
License
MIT License
Created over 7 years ago
Updated about 1 year ago

nanamake/r22sdf

nanamake

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Pipeline FFT Implementation in Verilog HDL

vcd2json

Create WaveJSON from VCD file. WaveDrom can convert it to timing diagram.

avr_cpu

AVR CPU Core Implementation in Verilog HDL.

pseudo_hdl

Pseudo HDL and its simulator written in Python.