alexforencich/verilog-i2c alexforencich/verilog-i2c

  • Stars
    star
    485
  • Rank 90,377 (Top 2 %)
  • Language Verilog
  • License
    MIT License
  • Created over 10 years ago
  • Updated 3 months ago
Twitter logo Share LinkedIn logo Share Facebook logo Share
alexforencich/verilog-i2c
github

alexforencich

Reviews

There are no reviews yet. Be the first to send feedback to the community and the maintainers!

Repository Details

Verilog I2C interface for FPGA implementation

Verilog I2C interface

For more information and updates: http://alexforencich.com/wiki/en/verilog/i2c/start

GitHub repository: https://github.com/alexforencich/verilog-i2c

Introduction

I2C interface components. Includes full MyHDL testbench with intelligent bus cosimulation endpoints.

Documentation

i2c_init module

Template module for peripheral initialization via I2C. For use when one or more peripheral devices (i.e. PLL chips, jitter attenuators, clock muxes, etc.) need to be initialized on power-up without the use of a general-purpose processor.

i2c_master module

I2C master module with AXI stream interfaces to control logic.

i2c_master_axil module

I2C master module with 32-bit AXI lite slave interface.

i2c_master_wbs_8 module

I2C master module with 8-bit Wishbone slave interface.

i2c_master_wbs_16 module

I2C master module with 16-bit Wishbone slave interface.

i2c_slave module

I2C slave module with AXI stream interfaces to control logic.

i2c_slave_axil_master module

I2C slave module with parametrizable AXI lite master interface.

i2c_slave_wbm module

I2C slave module with parametrizable Wishbone master interface.

Source Files

axis_fifo.v             : AXI stream FIFO
i2c_init.v              : Template I2C bus init state machine module
i2c_master.v            : I2C master module
i2c_master_axil.v       : I2C master module (32-bit AXI lite slave)
i2c_master_wbs_8.v      : I2C master module (8-bit Wishbone slave)
i2c_master_wbs_16.v     : I2C master module (16-bit Wishbone slave)
i2c_slave.v             : I2C slave module
i2c_slave_axil_master.v : I2C slave module (parametrizable AXI lite master)
i2c_slave_wbm.v         : I2C slave module (parametrizable Wishbone master)

Testing

Running the included testbenches requires MyHDL and Icarus Verilog. Make sure that myhdl.vpi is installed properly for cosimulation to work correctly. The testbenches can be run with a Python test runner like nose or py.test, or the individual test scripts can be run with python directly.

Testbench Files

tb/axil.py           : MyHDL AXI4 lite master and memory BFM
tb/axis_ep.py        : MyHDL AXI Stream endpoints
tb/i2c.py            : MyHDL I2C master and slave models
tb/wb.py             : MyHDL Wishbone master model and RAM model

More Repositories

1

verilog-ethernet

Verilog Ethernet components for FPGA implementation
Verilog
1,993
star
2

verilog-axi

Verilog AXI components for FPGA implementation
Verilog
1,360
star
3

verilog-pcie

Verilog PCI express components
Verilog
1,010
star
4

verilog-axis

Verilog AXI stream components for FPGA implementation
Python
722
star
5

verilog-uart

Verilog UART
Verilog
390
star
6

cocotbext-axi

AXI interface modules for Cocotb
Python
208
star
7

verilog-lfsr

Fully parametrizable combinatorial parallel LFSR/CRC module
Python
135
star
8

cocotbext-pcie

PCI express simulation framework for Cocotb
Python
126
star
9

xboot

XBoot Extensible Bootloader
C
125
star
10

verilog-wishbone

Verilog wishbone components
Python
104
star
11

verilog-cam

Verilog Content Addressable Memory Module
Verilog
97
star
12

verilog-dsp

Verilog digital signal processing components
Python
96
star
13

cocotbext-eth

Ethernet interface modules for Cocotb
Python
51
star
14

xfcp

Extensible FPGA control platform
Verilog
51
star
15

ftjrev

JTAG reverse engineering software for FTDI compatible cables
C
49
star
16

pin-uart

FPGA board-level debugging and reverse-engineering tool
Tcl
28
star
17

cocotbext-i2c

I2C models for cocotb
Python
26
star
18

verilog-ft245

Verilog FT245 to AXI stream interface
Python
26
star
19

dma-bench

Verilog
25
star
20

verilog-mersenne

Verilog implementation of Mersenne Twister PRNG
Python
24
star
21

cocotbext-uart

UART models for cocotb
Python
22
star
22

python-hpgl

Python HPGL parsing library
Python
18
star
23

python-vxi11

Provides a VXI-11 driver for controlling instruments over Ethernet
Python
12
star
24

fpga-utils

Various utilities for working with FPGAs
Python
10
star
25

verilog-flowgen

Ethernet flow generator framework
Python
9
star
26

templates

Templates for Embedded Development
C++
8
star
27

hdg2000

HDG2000
Python
7
star
28

binaryninja-m68k

Motorola 68k architecture support for binary ninja
Python
7
star
29

zigbee-terminal

Cross-platform ZigBee terminal
C++
7
star
30

xgrid

AVR XMEGA Grid Computing
C++
7
star
31

verilog-priorityqueue

3
star
32

groupmgr

Group manager plugin for Dokuwiki
PHP
2
star
33

verilog-hashtable

2
star
34

xmlconf

C
2
star