Zeeshan Rafique (@zeeshanrafique23)
github

zeeshanrafique23

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  • Stars
    star
    60
  • Global Rank 298,552 (Top 11 %)
  • Followers 103
  • Following 25
  • Registered over 6 years ago
  • Most used languages
    Verilog     50.0 %
    SystemVerilog     16.7 %
    CSS
         16.7 %
    XSLT     16.7 %
  • Location πŸ‡ͺπŸ‡Έ Spain
  • Country Total Rank 903
  • Country Ranking
    Verilog     10
    SystemVerilog     11
    XSLT     15
    CSS
         829

Top repositories

1

mdu

M-extension for RISC-V cores.
Verilog
21
star
2

RV32I-Logisim

RV32I single cycle simulation on open-source software Logisim.
16
star
3

zeeshanrafique23

My GitHub Profile README. Don't just fork, star it, so others can find it too! πŸ‘€
9
star
4

rv-compressed

Compressed instruction decoder (C-extension) for RISC-V Cores.
Verilog
4
star
5

zeeshanrafique23.github.io

My portfolio.
CSS
3
star
6

RV32I-Chisel

This repo contains the files of the RV32I Single-cycle processor in CHISEL.
XSLT
2
star
7

Chisel-Generated-Verilog-RV32I

This repo contains chisel generated Verilog code.
Verilog
2
star
8

Buraq-mini

RISC-V 5-stage 32-bit (RV32IM) processor.
SystemVerilog
1
star
9

tcl

This repo contains the basic programs and practice code for tcl beginners.
1
star