Yasna Katebzadeh (@yasnakateb)
github

yasnakateb

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  • Stars
    star
    67
  • Global Rank 277,624 (Top 10 %)
  • Followers 37
  • Following 33
  • Registered over 6 years ago
  • Most used languages
    Verilog     68.8 %
    HTML
         6.3 %
    Scala
         6.3 %
    Dart
         6.3 %
    Rust
         6.3 %
    C
         6.3 %
  • Location 🇪🇸 Spain
  • Country Total Rank 154,545
  • Country Ranking
    Verilog     8
    Scala
         76
    Rust
         116
    Dart
         377
    C
         1,681
    HTML
         3,958

Top repositories

1

PipelinedARM

💎 A 32-bit ARM Processor Implementation in Verilog HDL
Verilog
16
star
2

Chatroom

🗣 Chatroom in Rust
Rust
14
star
3

NoCRouter

👶🏻 My first baby steps into the world of NoC
Verilog
8
star
4

CGRAs

Coarse Grained Reconfigurable Arrays with Chisel3
Scala
8
star
5

MIPSProcessor

🔮 A 32-bit MIPS Processor Implementation in Verilog HDL
Verilog
5
star
6

PipelinedMIPS

🔮 A 16-bit MIPS Processor Implementation in Verilog HDL
Verilog
4
star
7

WMController

✨🐾✨ A Control System for Washing Machine in Verilog HDL
Verilog
3
star
8

USSalPrediction

💰 Salary prediction
HTML
1
star
9

Blinky

💡A Quartus II project testing the functionality of the Altera Cyclone IV EP4CE6E22C8N board
Verilog
1
star
10

ChiselNotes

Chisel3 examples
Verilog
1
star
11

UARTCommunication

☎️ UART Communication Implementation in Verilog HDL
Verilog
1
star
12

Dartris

🏳️ A simple Tetris Game in Dart. Just for fun.
Dart
1
star
13

MSCAllocator

A simple allocator for experimental purposes
C
1
star
14

SdramController

🛠 A SDRAM controller in Verilog HDL
Verilog
1
star
15

AES

🔐 Hardware Implementation Of AES Algorithm in Verilog HDL
Verilog
1
star
16

FIFOMemory

📍 A FIFO Memory Implementation in Verilog HDL
Verilog
1
star