Icser (@xie-1399)
github

xie-1399

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  • Stars
    star
    35
  • Global Rank 438,984 (Top 16 %)
  • Followers 4
  • Following 3
  • Registered over 4 years ago
  • Most used languages
    Scala
         31.3 %
    Python
         25.0 %
    Java
         18.8 %
    Verilog     12.5 %
    C
         6.3 %
    Cuda     6.3 %
  • Location 🇨🇳 China
  • Country Total Rank 56,459
  • Country Ranking
    Scala
         214
    Cuda     298
    Verilog     316

Top repositories

1

B-Lib

some useful libs using in the SpinalHDL
Scala
4
star
2

Attention-Based-Accelerator

Implement some hardware NN accelerators using spinalHDL
Python
3
star
3

Nvdla_Spinal

using the SpinalHDL to rebuild the NVDLA Arch
Verilog
3
star
4

Brief-Chip

The Brief Chip is a Simple Soc project written in Spinal HDL , include a 3 stages RISCV CPU and a CNN Accelerator with RS Dataflow as Peripheral
Scala
3
star
5

MLArch

ML Systems And Computer Arch
Python
2
star
6

Awesome-Paper

The trace of Paper Reading about DSA、GPU、LLM and AI System
2
star
7

HardWareHDL

Hardware HDL language about Spinal HDL and Chisel
Scala
2
star
8

Betsy

The Implement of the Systolic Array Accelerator
Scala
2
star
9

StylePatch

the source code of the StylePatch（a adversarial patch attack method using the local style fusion）
Python
2
star
10

B-Core

a five stage riscv core using SpinalHDL and some common libs
Scala
1
star
11

Race

比赛项目代码
Java
1
star
12

GPGPU

The trace to study in the GPU Arch and Cuda Programming
Cuda
1
star
13

CS-Arch

The Fantastic RISCV Zone
C
1
star
14

RVGenerator

use to generate the random RISC-V instructions to test the CPU
Python
1
star
15

JavaSE

上传JavaSE项目
Java
1
star
16

AndroidCode

用于上传有关Android的代码
Java
1
star
17

ICTools

Here is some really useful tools for the ASIC/FPGA Design
Verilog
1
star
18

Multimodal-VLP

The Implement of MultiModal VLP Transformers Alg
1
star