Simon Southwell (@wyvernSemi)
github

wyvernSemi

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  • Stars
    star
    255
  • Global Rank 101,592 (Top 4 %)
  • Followers 103
  • Registered about 8 years ago
  • Most used languages
    C
         33.3 %
    C++
         28.6 %
    Verilog     19.0 %
    Assembly
         9.5 %
    Python
         4.8 %
    Java
         4.8 %
  • Location 🇬🇧 United Kingdom
  • Country Total Rank 7,220
  • Country Ranking
    Verilog     27
    Assembly
         141
    C
         304
    C++
         551
    Java
         6,473

Top repositories

1

pcievhost

PCIe (1.0a to 2.0) Virtual host model for verilog
C
71
star
2

vproc

Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
C
39
star
3

riscV

Open source ISS and logic RISC-V 32 bit project
C++
31
star
4

usbModel

USB virtual model in C++ for Verilog
C++
25
star
5

winfilter

WinFilter graphical FIR filter design program
C
12
star
6

tcpIpPg

10GbE XGMII TCP/IPv4 packet generator for Verilog
C++
11
star
7

cpu8051

Intel(R) 8051 Instruction Set Simulator
C
9
star
8

eccExamples

Error correction and detection example Verilog (hamming and Reed-Solomon) to accompany presentation material
Verilog
9
star
9

mico32

LatticeMico32 instruction set simulator project
C++
8
star
10

cpu6502

A 6502 Instruction Set Simulator
Assembly
7
star
11

jfif

JFIF and JPEG file decoder software
C++
7
star
12

vslzw

Verilog Decoder implementing a simple LZW algorithm,
Verilog
5
star
13

sparc

Sparc version 8 Instruction Set Simulator
Assembly
4
star
14

mem_model

High speed C/C++ based behavioural Verilog memory model
C
4
star
15

firfilter

Verilog finite impulse response filter
Verilog
3
star
16

kernel_module

Linux Kernel Module Template
C
2
star
17

slzw

Simple LZW codec in C
Java
2
star
18

mem_subsys

Memory sub-system component project (cache/MMU)
1
star
19

pli_test

Test of VProc and mem_model PLI components in Aldec simulators
Verilog
1
star
20

bmp

Command line bitmap manipulation utility
C
1
star
21

lm32fpga

FPGA development board (DE1) targetted lm32 based systems design for Verilog
Python
1
star
22

CoSim

OSVVM submodule for Co-simulation features
C++
1
star