Syeda Rafia Fizza Naveed (@syedarafia13)
github

syedarafia13

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  • Stars
    star
    11
  • Global Rank 920,445 (Top 32 %)
  • Followers 9
  • Following 16
  • Registered over 3 years ago
  • Most used languages
    Verilog     33.3 %
    SystemVerilog     33.3 %
    C++
         33.3 %
  • Location 🇵🇰 Pakistan
  • Country Total Rank 2,543
  • Country Ranking
    SystemVerilog     8
    Verilog     10
    C++
         471

Top repositories

1

RISCV-RV32I-LOGISIM

RISCV is an open source software.
Verilog
3
star
2

5-STAGE-PIPELINING-RV32I

C++
1
star
3

system-verilog

SystemVerilog
1
star
4

RISCV-RV32I-CORE

C++
1
star
5

verilog-practice

Verilog
1
star
6

RISCV-CORE-FPGA

This repository contains RISCV (RV32I) Single Cycle Processor RTL design in SystemVerilog and Testbench in C++ for fpga.
SystemVerilog
1
star