James E. Stine (@stineje)
github

stineje

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  • Stars
    star
    87
  • Global Rank 229,741 (Top 8 %)
  • Followers 42
  • Following 20
  • Registered about 8 years ago
  • Most used languages
    Tcl     25.0 %
    C
         16.7 %
    Verilog     8.3 %
    SystemVerilog     8.3 %
    Assembly
         8.3 %
    HTML
         8.3 %
    Perl
         8.3 %
    Python
         8.3 %
    TeX
         8.3 %
  • Location πŸ‡ΊπŸ‡Έ United States
  • Country Total Rank 55,176
  • Country Ranking
    Tcl     28
    SystemVerilog     258
    Verilog     742
    Assembly
         1,035
    Perl
         2,104
    TeX
         3,044

Top repositories

1

sky130RHBDlib

Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130
Tcl
27
star
2

CharLib

Open-source repository for a standard-cell library characterizer using complete open-source tools
Python
14
star
3

sky130_cds

This repository is an open-source version of SKY130 to help facilitate use of Cadence Design System tools for use with Skywater 130 Process Design Kit
Tcl
12
star
4

ecen4303F23

Files associated with Digital Integrated Circuits (ecen4303) at Oklahoma State University
Tcl
9
star
5

ecen4243S24

Spring 2023 ecen4243 Computer Architecture Lab Material
HTML
6
star
6

osu-riscv

OSU Datapath/Control RV32 Single-Cycle and Pipelined Architecture in SV
Assembly
3
star
7

prefix_adders

Prefix adder generators for Verilog
Perl
3
star
8

dldfall2023

This repository contains information about Digital Logic Design (ecen 3233) laboratory elements for Fall 2023.
TeX
3
star
9

HSCA_S24

High-Speed Computer Arithmetic Spring 2024 at Oklahoma State University
C
3
star
10

xchiplogo

This is chiplogo a logo generator for VLSI chips.
C
2
star
11

SpringerBookArith04

These are files from my 2004 book, "Digital Computer Arithmetic Datapath Design Using Verilog HDL"
Verilog
2
star
12

DES

Open-source DES library in SystemVerilog used during ecen3233 at Oklahoma State University F21 and S22 semesters
SystemVerilog
1
star