Discover @stineje Open Source projects

James E. Stine (@stineje)

stineje

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Global Rank 229,741 (Top 8 %)
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Registered about 8 years ago
Most used languages

Tcl 25.0 %

C
16.7 %

Verilog 8.3 %

Perl
8.3 %

Python
8.3 %

TeX
8.3 %

SystemVerilog 8.3 %

Assembly
8.3 %

HTML
8.3 %
Location 🇺🇸 United States
Country Total Rank 55,176
Country Ranking

Tcl 28

SystemVerilog 258

Verilog 742

Assembly
1,035

Perl
2,104

TeX
3,044

sky130RHBDlib

Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130

CharLib

Open-source repository for a standard-cell library characterizer using complete open-source tools

sky130_cds

This repository is an open-source version of SKY130 to help facilitate use of Cadence Design System tools for use with Skywater 130 Process Design Kit

ecen4303F23

Files associated with Digital Integrated Circuits (ecen4303) at Oklahoma State University

ecen4243S24

Spring 2023 ecen4243 Computer Architecture Lab Material

osu-riscv

OSU Datapath/Control RV32 Single-Cycle and Pipelined Architecture in SV

prefix_adders

Prefix adder generators for Verilog

dldfall2023

This repository contains information about Digital Logic Design (ecen 3233) laboratory elements for Fall 2023.

HSCA_S24

High-Speed Computer Arithmetic Spring 2024 at Oklahoma State University

xchiplogo

This is chiplogo a logo generator for VLSI chips.

SpringerBookArith04

These are files from my 2004 book, "Digital Computer Arithmetic Datapath Design Using Verilog HDL"

DES

Open-source DES library in SystemVerilog used during ecen3233 at Oklahoma State University F21 and S22 semesters