Stafford Horne (@stffrdhrn)
github

stffrdhrn

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  • Stars
    star
    401
  • Global Rank 69,723 (Top 3 %)
  • Followers 116
  • Following 39
  • Registered almost 12 years ago
  • Most used languages
    Verilog     56.7 %
    Shell
         10.0 %
    Eagle     6.7 %
    Makefile     6.7 %
    C
         6.7 %
    Ruby
         3.3 %
    C++
         3.3 %
    Scheme
         3.3 %
    PHP
         3.3 %
  • Location 🇯🇵 Japan
  • Country Total Rank 1,583
  • Country Ranking
    Verilog     1
    Eagle     5
    Scheme
         72
    Makefile     78
    Shell
         753
    PHP
         1,231
    C
         1,490
    Ruby
         1,520
    C++
         4,131

Top repositories

1

sdram-controller

Verilog SDRAM memory controller
Verilog
251
star
2

uart

Verilog uart receiver and transmitter modules for De0 Nano
Verilog
16
star
3

kicad-spice-demo

Demo of simulating kicad schematics in spice
Eagle
11
star
4

tls-examples

TLS access example code snippets
Makefile
10
star
5

adc_interface

Verilog ADC interface for adc128s022 found in De0 Nano
Verilog
9
star
6

intelhex

Intel HEX file generator
Ruby
8
star
7

ac97

opencores ac97 controller verilog core
Verilog
7
star
8

wb_dma

Wishbone dma/bridge controller in verily
Verilog
6
star
9

or1k-toolchain-build

OpenRISC toolchain build scripts
Shell
6
star
10

mor1kx-generic

mor1kx OpenRISC generic test harness support verilator and iverilog
Verilog
5
star
11

de0_nano-multicore

OpenRISC multicore SoC for De0 Nano
Verilog
4
star
12

adc_preamp

Kicad schematic for opamp based microphone preamp circuit used with my adc_interface project
Eagle
4
star
13

de0_nano

OpenRISC SOC for the De0 Nano FPGA dev board
Verilog
3
star
14

stffrdhrn.github.io

Github blog for stafford horne
C
3
star
15

fudosan

PHP, Twiiter Bootstrap, jQuery, CouchDB based webapp for managing real-estate property and client relationships
PHP
3
star
16

or1k-utils

linux initramfs, testing, openocd, and other random utils for openrisc
Shell
3
star
17

ompic

Open Multi-Processor Interrupt Controller - for OpenRISC
Verilog
2
star
18

junk

Dumping ground for test programs and ideas, mostly used for toolchain testing
Makefile
2
star
19

hostconfig

My backup of host and dot file config
Shell
2
star
20

cgen

architecture code generation used by binutils
Scheme
2
star
21

micron-cores

FuseSOC cores for micron verilog models
Verilog
2
star
22

digi-recorder

A digital recorder for fpga in verilog, tested on de0 nano.
Verilog
2
star
23

freemodelfoundry-cores

FuseSOC cores for free model foundry verilog models
2
star
24

verilator_tb_utils

Verilator test bench utils
C++
1
star
25

flipflop

Verilog flip flop project, basically hello world for De0 Nano
Verilog
1
star
26

beeper

Verilog wave generator and pulse width modulator (PWM) for De0 Nano
Verilog
1
star
27

wiredelay

A wire delay simulation verilog core
Verilog
1
star
28

berkeley-softfloat-2

Berkeley Softfloat 2c - with updates
C
1
star
29

egg_timer

Verilog egg timer for De0 Nano
Verilog
1
star
30

dram_tester

A testsuite for my dram controller
Verilog
1
star
31

intgen

An verilog core for testing CPU interrupts
Verilog
1
star