Shivani Shah (@shivanishah269)
github

shivanishah269

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  • Stars
    star
    99
  • Global Rank 208,502 (Top 8 %)
  • Followers 62
  • Following 6
  • Registered almost 9 years ago
  • Most used languages
    Verilog     75.0 %
    SystemVerilog     25.0 %
  • Location 🇮🇳 India
  • Country Total Rank 7,020
  • Country Ranking
    Verilog     7
    SystemVerilog     10

Top repositories

1

risc-v-core

This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover
Verilog
67
star
2

vsdfpga

Implementation of Mixed Signal SoC (RISCV based Core + PLL) on FPGA
SystemVerilog
8
star
3

FPGA_based_Multicore_Cache_Simuator

Cache-accel: FPGA Accelerated Multi-Core Cache Simulator
Verilog
8
star
4

DSP_ActiveNoiseCancellation

3
star
5

Encryption_Algorithm_RSA_on_FPGA

This project is done as a part of System Design with FPGA course.
Verilog
3
star
6

mpw5_cache

1
star