Sai Kaushik S (@sai-kaushik-s)
github

sai-kaushik-s

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  • Stars
    star
    29
  • Global Rank 505,517 (Top 18 %)
  • Followers 25
  • Following 21
  • Registered over 5 years ago
  • Most used languages
    Verilog     35.7 %
    Python
         28.6 %
    C
         14.3 %
    C++
         7.1 %
    Assembly
         7.1 %
    Lua
         7.1 %
  • Location 🇮🇳 India
  • Country Total Rank 21,829
  • Country Ranking
    Verilog     59
    Lua
         350
    Assembly
         419
    C
         3,025
    Python
         6,036

Top repositories

1

VLIW-Architecture

A Python - Verilog combination that simulates the working of a 32-bit 5-stage pipelined VLIW processor from input assembly code while monitoring the updates in the processor register file.
Verilog
6
star
2

NetList-Viewer-and-Simulator

A python program that parses a verilog netlist (.vm) files and generates a graph and simulates the file with user inputs.
Python
6
star
3

Sim-File-Generator

A python program that generates a .sim file from a input boolean expression.
Python
3
star
4

Computer-Networking-Practice

Python
2
star
5

VLSI-Design-Practice

C
2
star
6

16-bit-Kogge-Stone-Adder

Verilog
2
star
7

First-and-Follow

A python GUI application that computes the first and follow of non-terminals in a grammar
Python
2
star
8

Computer-Organization-and-Design-Practice

Assembly
1
star
9

64-bit-4-2-Compression-Dadda-Multiplier

Verilog
1
star
10

Operating-System-Practice

C
1
star
11

CS50-Introduction-to-Game-Development-Assignment

Lua
1
star
12

16-bit-5-2-Compression-Dadda-Multiplier

Verilog
1
star
13

32-bit-15-4-Compression-Dadda-Multiplier

Verilog
1
star
14

Design-and-Analysis-of-Algorithms-Practice

C++
1
star