Oded Yosef (@odedyo)
github

odedyo

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  • Stars
    star
    19
  • Global Rank 661,842 (Top 23 %)
  • Followers 1
  • Registered about 6 years ago
  • Most used languages
    Verilog     40.0 %
    VHDL     40.0 %
    C
         20.0 %
  • Location 🇮🇱 Israel
  • Country Total Rank 2,070
  • Country Ranking
    Verilog     1
    VHDL     2
    C
         462

Top repositories

1

Median-filter-verilog-

Design a median filter for a Generic RGB image.
Verilog
12
star
2

Clock_Divider-

A frequency divider of 50 MHz to 4 frequencies with a different Duty cycles
VHDL
3
star
3

Carry_select_adder

16 bit adder
Verilog
1
star
4

DriverForDCMotor

Driver and electrical circuit for a DC Motor
C
1
star
5

ALU_fpga

Arithmetic logic unit on FPGA
VHDL
1
star