@nguyenquanicd
github

nguyenquanicd

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  • Stars
    star
    44
  • Global Rank 373,242 (Top 13 %)
  • Followers 64
  • Registered over 7 years ago
  • Most used languages
    SystemVerilog     57.1 %
    Verilog     21.4 %
    C++
         14.3 %
    Python
         7.1 %
  • Location ๐Ÿ‡ป๐Ÿ‡ณ Vietnam
  • Country Total Rank 1,298
  • Country Ranking
    SystemVerilog     1
    Verilog     4
    C++
         247
    Python
         2,304

Top repositories

1

UvmEnvUartApb

This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetigating the UVM env.
SystemVerilog
18
star
2

FirstX2P

This is the AXI-to-APB bridge which only supports convert AXI-32bit to APB-32 bit
SystemVerilog
6
star
3

VG_RTL

All RTL codes of VG project
SystemVerilog
5
star
4

AllArbiterRTLCode

RTL code of some arbitration algorithm
Verilog
5
star
5

SystemCScpuCA

This is the example of Cycle Accurate (CA) model. It is the Simple CPU (SCPU) is described in SystemC language.
C++
4
star
6

VLSITech_Study

3
star
7

AsyncFIFO

An asyncchronous FIFO
SystemVerilog
3
star
8

apbUartUvmSystemC

A SystemC UVM environment for UART-APB
C++
3
star
9

AXI4VIP

AXI4 VIP supports both AXI master and slave.
SystemVerilog
3
star
10

Aes128_ECB_CBC_CFB_OFB_CTR

AES128 IP core supports ECB, CBC, CFB, OFB and CTR mode
SystemVerilog
2
star
11

AxiVIP

An AxiVIP supports both master and slave mode
SystemVerilog
2
star
12

FPGA_Starter

Xilinx FPGA Starter
2
star
13

SynchronousFIFO

Synchronous FIFO with the configured parameters
Verilog
1
star
14

JtagProgramming

This is the example to explain "How to program a memory via JTAG?"
SystemVerilog
1
star
15

DEScore

DES Encipher Decipher IP core
Verilog
1
star
16

RegRTLGen

This is the open source tool which is used to create the System Verilog RTL code of register module
Python
1
star