Muneeb Ulla Shariff (@muneebullashariff)
github

muneebullashariff

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  • Stars
    star
    152
  • Global Rank 151,758 (Top 6 %)
  • Followers 96
  • Following 9
  • Registered almost 9 years ago
  • Most used languages
    SystemVerilog     66.7 %
    Python
         22.2 %
    Vim Script
         11.1 %
  • Location 🇮🇳 India
  • Country Total Rank 4,124
  • Country Ranking
    SystemVerilog     1
    Vim Script
         64
    Python
         6,064

Top repositories

1

axi4_vip

Verification IP for APB protocol
SystemVerilog
42
star
2

i2c_vip

Verification IP for I2C protocol
SystemVerilog
29
star
3

apb_vip

Verification IP for APB protocol
SystemVerilog
13
star
4

uart_vip

Verification IP for UART protocol
SystemVerilog
13
star
5

spi_vip

Verification IP for SPI protocol
SystemVerilog
12
star
6

pulpino_soc_uvm_testbench

UVM testbench for verifying the Pulpino SoC
SystemVerilog
12
star
7

PeakRDL-pdf

Converts the SystemRDL data into pdf Register specification
Python
11
star
8

best_coding_practices

Describes the best coding practices and guidelines
Vim Script
6
star
9

jtag_vip

Verification IP for JTAG protocol
2
star
10

PeakRDL-svh

Used for creating the systemverilog header files, which contains the defines for the registers
Python
2
star
11

i2s_vip

Verification IP for I2S Protocol
1
star
12

gpio_vip

Verification IP for GPIO protocol
1
star
13

uvm_register_code_generator

The idea is to develop the python script to automate the RAL generation
1
star