Meinhard Kissich (@meiniKi)
github

meiniKi

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  • Stars
    star
    82
  • Global Rank 239,858 (Top 9 %)
  • Followers 15
  • Following 11
  • Registered over 7 years ago
  • Most used languages
    SystemVerilog     42.9 %
    Arduino     28.6 %
    Assembly
         14.3 %
    Verilog     14.3 %
  • Location 🇦🇹 Austria
  • Country Total Rank 4,016
  • Country Ranking
    SystemVerilog     1
    Arduino     11
    Verilog     17
    Assembly
         51

Top repositories

1

FazyRV

A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
SystemVerilog
66
star
2

logIP

Logic Analyzer IP Core
SystemVerilog
5
star
3

smsbox

This fun project receives text messages (sms) and prints them via the thermal printer
Arduino
3
star
4

RV32I_SC_Logisim

A minimalistic single-cycle RISC-V platform for demonstrational and educational purposes in Logisim Evolution.
Verilog
2
star
5

Nokia_5110_Design_Clock

[WIP] A little project using a Nokia 5110 display and an Arduino Nano + DS3231 RTC to build a neat clock.
Arduino
2
star
6

tt06-FazyRV-ExoTiny

SystemVerilog
1
star
7

FazyRV-ExoTiny

Assembly
1
star