Discover @lexgolovchenko Open Source projects

Aleksey Golovchenko (@lexgolovchenko)

lexgolovchenko

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Registered over 10 years ago
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SystemVerilog 75.0 %

Makefile 25.0 %
Location 🇷🇺 Russia
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SystemVerilog 17

Makefile 202

emif16-avmm-bridge

Module for connect TI DSP to Altera Qsys Interconnect through EMIF16 interface

avmm-lvds-bridge

Cores for transfer Avalon-MM transaction through LVDS SERDES interface

altera-makefiles

Makefiles & scripts for Altera FPGA projects

avalon-1wire-master

1-wire bus master core with Altera Avalon-MM slave interface