Jaspreet Singh (@jaspreetsingh009)
github

jaspreetsingh009

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  • Stars
    star
    71
  • Global Rank 265,383 (Top 10 %)
  • Followers 25
  • Following 4
  • Registered about 12 years ago
  • Most used languages
    VHDL     50.0 %
    JavaScript
         20.0 %
    HTML
         10.0 %
    C
         10.0 %
    Python
         10.0 %
  • Location 🇮🇳 India
  • Country Total Rank 9,326
  • Country Ranking
    VHDL     6
    C
         385
    HTML
         1,236

Top repositories

1

Digital-Phase-Locked-Loop-PLL

Single Phase Digital PLL design using TI's Delfino Launchpad
C
23
star
2

webui_msp430

A web based user interface for TI's MSP430FR5739 launchpad
HTML
22
star
3

ADC_LCD_FPGA

ADC & LCD Interfacing using Verilog & VHDL
VHDL
10
star
4

nRF24L01-Web-Data-Logger

MSP430 and Nordic nRF24L01+ based web data logger
JavaScript
4
star
5

python_msp430

Python GUI with MSP430FR5739 Launchpad Accelerometer
Python
3
star
6

fpga_data_logger

FPGA based data logger (LCD, ADC, UART & I2C)
VHDL
3
star
7

ADC_UART

Interfacing ADC128S022, 8-Channel, 12-bit A/D Converter and implementing UART with FPGA
VHDL
3
star
8

IoT_FRDM

Web UI based data acquisition & control unit for FRDM-KL25z Development board
JavaScript
1
star
9

UART_FPGA

UART module implemented on an FPGA using VHDL
VHDL
1
star
10

FPGA_PWM_CONTROL_DESIGN

PWM Control Loop design for Synchronous Boost Converter using FPGA
VHDL
1
star