Heqing Huang (@feipenghhq)
github

feipenghhq

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  • Stars
    star
    17
  • Global Rank 708,350 (Top 25 %)
  • Followers 10
  • Following 9
  • Registered almost 8 years ago
  • Most used languages
    Verilog     33.3 %
    Python
         22.2 %
    SystemVerilog     22.2 %
    Scala
         11.1 %
    Tcl     11.1 %
  • Location 🇺🇸 United States
  • Country Total Rank 135,062
  • Country Ranking
    SystemVerilog     114
    Tcl     405
    Verilog     735
    Scala
         1,673

Top repositories

1

AppleRISCV

A RISCV CPU written in Spinalhdl.
Scala
5
star
2

Verilog-Design-Example

Writing my own Verilog code for the book <Advanced Chip Design Practical Examples in Verilog>
SystemVerilog
5
star
3

FPGA-Utils

FPGA Utility
Tcl
1
star
4

verilog-amba-bus

AMBA (AHB/APB) related IP written in Verilog
Python
1
star
5

verilog-uart

Uart IP written in Verilog
Verilog
1
star
6

pycsr

Control and Status Register (CSR) using python
Python
1
star
7

spinalhdl-mcu-ip

Verilog
1
star
8

verilog-misc-ip

miscellaneous ip written in verilog
Verilog
1
star
9

FPGA-BUS

Various bus design for FPGA projects
SystemVerilog
1
star