RISCV-32BitCPU

A verilog (FPGA based) project & Logisim simulation for creating a functional RISC-V 32-bit CPU running all instructions.

chess-gui-multiplayer

A simple multiplayer GUI chess game in C++

FPGA-VerilogHDL-Course

Some Examples and their solutions in VerilogHDL targeted to DE1 FPGA board.