Eric (@erihsu)
github

erihsu

Twitter logo Share LinkedIn logo Share Facebook logo Share
  • Stars
    star
    148
  • Global Rank 155,276 (Top 6 %)
  • Followers 36
  • Following 61
  • Registered over 7 years ago
  • Most used languages
    Rust
         60.0 %
    Python
         15.0 %
    Perl
         5.0 %
    V     5.0 %
    Verilog     5.0 %
    SystemVerilog     5.0 %
    C
         5.0 %
  • Location 🇨🇳 China
  • Country Total Rank 24,743
  • Country Ranking
    V     5
    Verilog     29
    SystemVerilog     82
    Rust
         316
    Perl
         463

Top repositories

1

INT_FP_MAC

INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
Verilog
79
star
2

Sym-CTS

symmetric clock tree synthesis for NTV IC design
Python
10
star
3

tf-parser

Technology file parser in Rust
Rust
9
star
4

mincost

A collection of modern heuristic optimization framework written in Rust
Rust
9
star
5

liberty2json

Convert Liberty(.lib) file into json, inspired by skywater-pdk
Rust
7
star
6

vgg16_quantization

The tensorflow vgg16 quantization implementation
Python
6
star
7

gds2-io

GDSII format IO utils
Rust
6
star
8

def_parser

DEF5.7 specification parser in Rust
Rust
4
star
9

lef-parser

Library Exchange Format(LEF) parser in Rust
Rust
2
star
10

sv_for_verification_notes

recording my notes about SystemVerilog for Verification
2
star
11

TinySoC

Arm cortex-m3 based SoC implementation used for simple car plane recognization
V
2
star
12

svfmt

systemverilog format
Rust
2
star
13

lutxt

lutxt is a plaint lookup table format which contains timing variation information for standard cell characterization
Python
1
star
14

vcd-io

VCD spec IO
Rust
1
star
15

SymCTS-rs

Rust
1
star
16

xor_encrypt

Simple xor encrypt matrix design and verification both in systemverilog
SystemVerilog
1
star
17

cts-plugin

Rust
1
star
18

instlist

Rust
1
star
19

tree-sitter-riscvasm

tree sitter for riscv assembly
C
1
star
20

sv_check

Parser for SystemVerilog files
Rust
1
star
21

Paper_Reproduction

reproduction paper research in low voltage clock tree design
Perl
1
star