Mazen Ahmed (@djzenma)
github

djzenma

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Top repositories

1

RV32IC-CPU

Implementation of the RISC-V 32 bit Integer and Compressed Instructions in Verilog.
Verilog
14
star
2

2-FPGAs-UART-Protocol

Transmitter and Receiver FPGAs connected using the UART Protocol to execute arithmetic operations and display the inputs on the transmitter's 7 Segment Display as well as the result on the Receiver's 7 Segments Display.
HTML
8
star
3

ECG-Heart-Monitor-STM32-TFLite

ECG Heart Monitor and Disease Detection using TensorFlow Lite on STM32 Microcontroller
C
6
star
4

Tomasulo-Simulation-Algorithm

Implementation of the Tomasulo Algorithm used in nowadays CPUs.
Java
3
star
5

TFLite-Applications-And-Models

TFLite applications: Optimized .tflite models (i.e. lightweight and low latency) and code to run directly on your Microcontroller!
3
star
6

RISCV-32IC-Sim

RISC-V 32IC Disassembler and Simulator
Java
2
star
7

DM-Cache-Simulator

Direct Map Cache Memory Simulator
C++
2
star
8

Peer-2-Peer-Instagram

C++
1
star
9

Macros-and-IO-Pins-Router

Routes the placed MACROS as well as the I/O PINS from any LEF and DEF files and writes the result in a DEF file.
Java
1
star
10

Warzone

Advanced Programming Practices Project @ Concordia University
Java
1
star
11

Raptor-SoC-TFLite-Hello-World

Tensorflow Lite Hello World project for Raptor SoC (efabless.com)
C++
1
star
12

Tomasulo-Simulation-Front-End

Simulation For Tomasolo's Algorithm
JavaScript
1
star
13

A-Star-Integrated-Circuit-Routing

A Star Algorithm used to route pins using Metal 1, Metal 2 and Metal 3 wires.
Java
1
star
14

Unicorn-Companies-Dataset-EDA

Jupyter Notebook
1
star