Alessandro Dei Giudici (@deigiudi)
github

deigiudi

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  • Stars
    star
    6
  • Global Rank 1,300,168 (Top 45 %)
  • Followers 2
  • Registered almost 7 years ago
  • Most used languages
    VHDL     33.3 %
    Verilog     33.3 %
    C
         33.3 %
  • Location πŸ‡§πŸ‡ͺ Belgium
  • Country Total Rank 4,660
  • Country Ranking
    Verilog     8
    VHDL     24
    C
         596

Top repositories

1

kayrv32

A Verilog implementation of a RISC-V RV32I based microprocessor (classic 5-stage, in-order, single issue)
Verilog
2
star
2

PICassembler

Assembler and disassembler for ISA of Microchip PIC16F672A microcontroller.
C
1
star
3

PortingKlessydra

PULPino platform port (in SystemVerilog, RISC-V ISA) with Klessydra X0-v14 core (in VHDL) for operation on Zedboard.
VHDL
1
star