Siddharth J (@darthsider)
github

darthsider

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  • Stars
    star
    47
  • Global Rank 356,388 (Top 13 %)
  • Followers 3
  • Registered over 7 years ago
  • Most used languages
    SystemVerilog     75.0 %
    Verilog     25.0 %
  • Location ๐Ÿ‡ฎ๐Ÿ‡ณ India
  • Country Total Rank 13,809
  • Country Ranking
    SystemVerilog     3
    Verilog     151

Top repositories

1

UART

UART design in SV and verification using UVM and SV
SystemVerilog
38
star
2

SystemVerilog

SV testbench for simple designs
SystemVerilog
5
star
3

8-bit-RISC-CPU

A simple 8-bit RISC processor in verilog
Verilog
3
star
4

altera_fifo_ip_verification

SystemVerilog
1
star