Carlos Pantelides (@cpantel)
github

cpantel

Twitter logo Share LinkedIn logo Share Facebook logo Share
  • Stars
    star
    66
  • Global Rank 280,620 (Top 10 %)
  • Followers 24
  • Registered almost 12 years ago
  • Most used languages
    C
         26.3 %
    Verilog     21.1 %
    VHDL     15.8 %
    Assembly
         5.3 %
    Ruby
         5.3 %
    Shell
         5.3 %
    Erlang
         5.3 %
    TypeScript
         5.3 %
    JavaScript
         5.3 %
    Tcl     5.3 %

Top repositories

1

DVGHV

Designing Video Game Hardware in Verilog
Verilog
25
star
2

Forzando-Brutalmente-MD5

C
6
star
3

ceiot_base

JavaScript
6
star
4

freerange_vhdl

Examples and exercises from the Freerange VHDL book
VHDL
4
star
5

xzoom

My modifications to xzoom linux magnifier
C
3
star
6

MicroTerminalAES

C
2
star
7

Easy6502

Solutions for the beautyful tiny ebook from Nick Morgan
2
star
8

MQTT

An ambitious multi architecture multi platform multi sensor/actuator MQTT demo
1
star
9

leet

Leet generator in several languages
Ruby
1
star
10

VGARenderer

Render VGA from the output of a Verilog or VHDL simulation
Tcl
1
star
11

prog_fpgas

The nexys4ddr (vivado) port of https://github.com/simonmonk/prog_fpgas (ISE)
Verilog
1
star
12

TLSKillSwitch

C
1
star
13

Flash-via-SPI

Some experiments related to reading the flash memory of a broken router
C
1
star
14

TheZynqBook

Exercises from the book
VHDL
1
star
15

SMAUEC

Sistema de Monitoreo y Alerta del Uso Excesivo del Calefón
TypeScript
1
star
16

pmod_vga

1
star
17

HardwareMalwareAccelerator

VHDL
1
star
18

HardwareMalwareSupervisor

Verilog
1
star
19

playground

POCs, tips, recipes
Shell
1
star
20

codeMutator

Framework de testing por mutación de código
Erlang
1
star
21

PracticalBinaryAnalysis

How to study "Practical Binary Analysis: Build Your Own Linux Tools for Binary Instrumentation, Analysis, and Disassembly" book by Dennis Andriesse
Assembly
1
star
22

CESE-MAySC-2021

Trabajo práctico de la materia Microarquitecturas y Softcores CESE 2021
Verilog
1
star