R. Timothy Edwards (@RTimothyEdwards)
github

RTimothyEdwards

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  • Stars
    star
    1,142
  • Global Rank 26,031 (Top 1.0 %)
  • Followers 382
  • Registered almost 9 years ago
  • Most used languages
    Verilog     36.4 %
    C
         27.3 %
    Shell
         22.7 %
    Python
         9.1 %
    MATLAB
         4.5 %
  • Location πŸ‡ΊπŸ‡Έ United States
  • Country Total Rank 8,868
  • Country Ranking
    Verilog     136
    C
         435
    Python
         4,318
    Shell
         6,022
    MATLAB
         8,402

Top repositories

1

magic

Magic VLSI Layout Tool
C
400
star
2

open_pdks

PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open processes.
Python
250
star
3

qflow

Qflow full end-to-end digital synthesis flow for ASIC designs
C
165
star
4

netgen

Netgen complete LVS tool for comparing SPICE or verilog netlists
C
98
star
5

XCircuit

XCircuit circuit drawing and schematic capture tool
C
87
star
6

qrouter

Qrouter detail router for digital ASIC designs
C
50
star
7

irsim

IRSIM switch-level simulator for digital circuits
C
30
star
8

capiche

Parasitic capacitance analysis of foundry metal stackups
Python
11
star
9

ravenna_standalone

A lightweight version of the efabless Ravenna RISC-V processor chip design files for public access
Verilog
9
star
10

caravel_openframe_project

Example digital project for the Efabless Caravel "openframe" harness
Verilog
7
star
11

chaos_automaton

Chaos Automaton (efabless Caravel harness digital project)
Verilog
6
star
12

tutorial_layout

Repository of files associated with the webinar on analog layout using magic and klayout with Matt Venn.
Shell
6
star
13

tclftdi

Tcl/Tk console based test system for development boards with FTDI chips. Also supports GPIB and instrumentation over ethernet.
Shell
5
star
14

vsd_lvs_lab

Laboratory exercises for the VSD course on physical verification, part 5: LVS
Verilog
2
star
15

sky130_ef_ip__xtal_osc_32k

Low power, low speed (32.768kHz) crystal oscillator circuit for sky130 technology
Shell
2
star
16

vsd_drc_lab

Laboratory exercises for the VSD course on physical verification, part 3, DRC
Shell
2
star
17

striVe_sky130

The striVe chip (test vehicle for sky130) picoRV32 implementation
Verilog
2
star
18

sky130_ef_ip__samplehold

Analog 3.3V sample and hold circuit, with buffered output
Verilog
2
star
19

sky130_ef_ip__rdac3v_8bit

8-bit resistor ladder DAC with 3.3V output range
MATLAB
1
star
20

sky130_ef_ip__instramp

Instrumentation amplifier (analog IP example)
Verilog
1
star
21

sky130_ef_ip__ccomp3v

Continuous analog comparator, 1mV resolution
Verilog
1
star
22

sky130_ef_ip__xtal_osc_16M

High speed (16MHz) crystal oscillator in sky130 technology
Shell
1
star