R. Timothy Edwards (@RTimothyEdwards)
github

RTimothyEdwards

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  • Stars
    star
    1,303
  • Global Rank 23,801 (Top 0.9 %)
  • Followers 430
  • Registered over 9 years ago
  • Most used languages
    Verilog     33.3 %
    Shell
         29.6 %
    C
         22.2 %
    Python
         7.4 %
    Makefile     3.7 %
    MATLAB
         3.7 %
  • Location πŸ‡ΊπŸ‡Έ United States
  • Country Total Rank 8,868
  • Country Ranking
    Verilog     123
    C
         400
    Makefile     1,274
    Python
         4,180
    Shell
         5,196
    MATLAB
         5,447

Top repositories

1

magic

Magic VLSI Layout Tool
C
468
star
2

open_pdks

PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open processes.
Python
274
star
3

qflow

Qflow full end-to-end digital synthesis flow for ASIC designs
C
182
star
4

XCircuit

XCircuit circuit drawing and schematic capture tool
C
105
star
5

netgen

Netgen complete LVS tool for comparing SPICE or verilog netlists
C
104
star
6

qrouter

Qrouter detail router for digital ASIC designs
C
56
star
7

irsim

IRSIM switch-level simulator for digital circuits
C
30
star
8

capiche

Parasitic capacitance analysis of foundry metal stackups
Python
10
star
9

ravenna_standalone

A lightweight version of the efabless Ravenna RISC-V processor chip design files for public access
Verilog
8
star
10

tutorial_layout

Repository of files associated with the webinar on analog layout using magic and klayout with Matt Venn.
Shell
7
star
11

caravel_openframe_project

Example digital project for the Efabless Caravel "openframe" harness
Verilog
7
star
12

sky130_ef_ip__opamp

Instrumentation amplifier (analog IP example)
Verilog
7
star
13

chaos_automaton

Chaos Automaton (efabless Caravel harness digital project)
Verilog
5
star
14

tclftdi

Tcl/Tk console based test system for development boards with FTDI chips. Also supports GPIB and instrumentation over ethernet.
Shell
5
star
15

chipalooza_projects_1

Chipalooza challenge first test chip of projects
Makefile
5
star
16

sky130_ef_ip__xtal_osc_32k

Low power, low speed (32.768kHz) crystal oscillator circuit for sky130 technology
Shell
2
star
17

sky130_ef_ip__samplehold

Analog 3.3V sample and hold circuit, with buffered output
Verilog
2
star
18

sky130_ef_ip__rdac3v_8bit

8-bit resistor ladder DAC with 3.3V output range
MATLAB
2
star
19

sky130_ef_ip__cdac3v_12bit

12-bit capacitive DAC
Shell
2
star
20

vsd_lvs_lab

Laboratory exercises for the VSD course on physical verification, part 5: LVS
Verilog
1
star
21

sky130_ef_ip__biasgen

Current bias generator circuit for distributing bias currents to analog circuits.
Shell
1
star
22

contact_programmed_ROM_cells

Set of layouts for contact-programmed ROM values of various bit widths.
1
star
23

vsd_drc_lab

Laboratory exercises for the VSD course on physical verification, part 3, DRC
Shell
1
star
24

striVe_sky130

The striVe chip (test vehicle for sky130) picoRV32 implementation
Verilog
1
star
25

sky130_ef_ip__ccomp3v

Continuous analog comparator, 1mV resolution
Verilog
1
star
26

sky130_ef_ip__xtal_osc_16M

High speed (16MHz) crystal oscillator in sky130 technology
Shell
1
star
27

fracn_dll

Alternative version of the Caravel digital locked loop (DLL) with a fractional feedback divider
Verilog
1
star
28

sky130_ef_ip__rc_osc_16M

16MHz (nominal) current-starved ring oscillator
Shell
1
star