MIPS-Pipelined-Processor

This is a MIPS 5 stage 32-bit pipelined processor with Harvard architecture, which comes with an assembler to interpret instructions to supported OP codes.

InstabugLogin

InstaLogin is a simple login page with email and password validation for Instabug front-end coding challenge.

PDP-11

A simulation to PDP-11 microprocessor with modelsim, The design is a micro-programmed based with an average of 9 clock cycles per instruction.

EmanOthman21

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