Chun-Feng, Chen (@Chun-Feng)
github

Chun-Feng

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  • Stars
    star
    37
  • Global Rank 421,862 (Top 15 %)
  • Followers 10
  • Following 58
  • Registered about 9 years ago
  • Most used languages
    Verilog     50.0 %
    C
         33.3 %
    C++
         16.7 %
  • Location πŸ‡ΉπŸ‡Ό Taiwan
  • Country Total Rank 2,984
  • Country Ranking
    Verilog     44
    C
         205
    C++
         320

Top repositories

1

CACTI-6.0

ASIC simulation of Multi-ported Memory Module. And it can offer SRAM-based dual-port basic building block to support multiple read/write ports, and it can easily get the simulation result (like frequency, power consumption, and area... etc.).
C
15
star
2

CACTI-6.5

This tools offer many simulation of memory design detail parameter. Then you can setting these parameter to running result in your condition circumstance.
C++
12
star
3

LVT_Writes_Method

Live Value Table (LVT-based) techniques is increasing write ports method, and using table to track the latest address data.
Verilog
2
star
4

Block_RAM_Module_FPGAs

Block RAMs (BRAMs) provide two types: two ports or dual-ports mode on FPGAs.
Verilog
2
star
5

2R1W-Memory-Design

Here offer 2R1W-based building block to proposed methodology to create multi-ported memory design. And different design to support more multi-ported level growth tree.
Verilog
1
star
6

2015CA-Course-NCTU---MM

NCTU-2015 fall CA course final project task.
C
1
star