yu-zou/LRUCache

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Ada
Created over 5 years ago
Updated over 5 years ago

yu-zou/LRUCache

yu-zou

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Set-associative cache using pseudo bit-LRU replacement policy, written in C++ and sythesized with Vivado HLS.

DirectNVM

An open-source RTL NVMe controller IP for Xilinx FPGA.

dram_sim_model

A Xilinx DDR3 simulation model wrapper logic.

SudokuSolver

Jupyter Notebook

rtl_template

A template folder for Vivado RTL project, including .gitignore.