yu-zou/DirectNVM yu-zou/DirectNVM

  • This repository has been archived on 12/Feb/2023
  • Stars
    star
    40
  • Rank 680,660 (Top 14 %)
  • Language VHDL
  • Created almost 4 years ago
  • Updated almost 4 years ago
Twitter logo Share LinkedIn logo Share Facebook logo Share
yu-zou/DirectNVM
github

yu-zou

Reviews

There are no reviews yet. Be the first to send feedback to the community and the maintainers!

Repository Details

An open-source RTL NVMe controller IP for Xilinx FPGA.

More Repositories

1

dram_sim_model

A Xilinx DDR3 simulation model wrapper logic.
Coq
3
star
2

LRUCache

Set-associative cache using pseudo bit-LRU replacement policy, written in C++ and sythesized with Vivado HLS.
Ada
2
star
3

SudokuSolver

Jupyter Notebook
1
star
4

rtl_template

A template folder for Vivado RTL project, including .gitignore.
1
star