xiyurain/UltraMIPS-CPU xiyurain/UltraMIPS-CPU

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  • Language Verilog
  • Created over 3 years ago
  • Updated over 3 years ago
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xiyurain/UltraMIPS-CPU
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xiyurain

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Repository Details

A Dual-issue MIPS CPU core feature with 5-level-pipeline, cache, Branch Predictor, TLB, UNIX OS SoC.

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