verilog-to-routing/verilog-to-routing.github.io

Stars
6
Rank 2,539,965 (Top 51 %)
Language SCSS
Created over 8 years ago
Updated 8 months ago

verilog-to-routing/verilog-to-routing.github.io

verilog-to-routing

There are no reviews yet. Be the first to send feedback to the community and the maintainers!

Website for Verilog to Routing

vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research

tatum

Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits

libblifparse

Parsing library for BLIF netlists

libsdcparse

ezgl

vtr-buildbot

Buildbot Infrastructure for VTR