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vercors
The VerCors verification toolset for verifying parallel and concurrent softwareltsmin
The LTSmin model checking toolsetsylvan
Multi-core Decision Diagram (BDD/LDD) implementationdftcalc
DFTCalc: A Dynamic Fault Tree calculator for reliability and availabilityUrPal
UPPAAL Sanity CheckerDFTRES
Rare event simulation tool for Dynamic Fault Treesjsylvan
JNI Bindings for Sylvanppopp16
Multi-Core On-The-Fly SCC Decompositionattop
Attack Tree translator and analyzerRabin-SPIN2017
Explicit State Model Checking with Generalized Büchi and Rabin Automataltl2ba
iFM19-MessagePassingAbstr
Practical Abstractions for Automated Verification of Message Passing ConcurrencyAdt2Upp
Attack tree convertor from ADTool to Uppaalllmc
Low-Level Model Checkerlace
Work-stealing framework LaceRabin-STTT
Explicit State Model Checking with Generalized Büchi and Rabin AutomataFMCAD-2023
Artifact for the submission of our paper to FMCAD 2023BW-NFM2016
Bandwidth and Wavefront Reduction for Static Variable Ordering in Symbolic Reachability Analysissylvan-tacas2015
Experimental data of Sylvan (TACAS 2015 paper)distbdd-tacas16
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