• Stars
    star
    46
  • Rank 613,923 (Top 13 %)
  • Language Verilog
  • Created over 4 years ago
  • Updated 11 months ago

Reviews

There are no reviews yet. Be the first to send feedback to the community and the maintainers!

Repository Details

Experiments with Yosys cxxrtl backend

More Repositories

1

panologic-g2

Pano Logic G2 Reverse Engineering Project
Verilog
136
star
2

rt

A Full Hardware Real-Time Ray-Tracer
Verilog
89
star
3

math

SpinalHDL Hardware Math Library
Scala
76
star
4

fake_parallel_printer

Capture traffic on parallel printer port to USB
C++
70
star
5

panologic

PanoLogic Zero Client G1 reverse engineering info
Verilog
69
star
6

kv260_bringup

Temporary repo to gather information about the Kria KV260 board
Python
51
star
7

mr1

MR1 formally verified RISC-V CPU
Scala
50
star
8

gdbwave

GDB server to debug CPU simulation waveform traces
C
40
star
9

cisco-hwic-3g-cdma

Reverse Engineering of the Cisco HWIC-3G-CDMA PCB
Verilog
40
star
10

tomverbeure.github.io

HTML
36
star
11

bscan_tools

Various JTAG boundary scan tools
Python
32
star
12

aha363

Python
25
star
13

color3

Information about eeColor Color3 HDMI FPGA board
Verilog
25
star
14

ecp5_jtag

Use ECP5 JTAG port to interact with user design
Verilog
24
star
15

vexriscv_ocd_blog

Repo that shows how to use the VexRiscv with OpenOCD and semihosting.
Assembly
20
star
16

jtag_uart_example

Mini CPU design with JTAG UART support
Verilog
18
star
17

upduino

Verilog
18
star
18

intel_jtag_uart

A Python module to interact with an Intel JTAG UART
Python
18
star
19

usb_system

SpinalHDL USB system for the ULPI based Arrow DECA board
Assembly
18
star
20

pdm

Assembly
17
star
21

intel_jtag_primitive_blog

How to use the Intel JTAG primitive without using virtual JTAG
Verilog
16
star
22

arrow_deca

LED blink example design for the Arrow DECA FPGA board
Shell
15
star
23

fpga_quick_ram_update

Quickly update a bitstream with new RAM contents
Verilog
14
star
24

cube

Scala
14
star
25

sidechan

Side channel communication test within an FPGA
Verilog
11
star
26

yosys_gatemap

An example that shows how to map a design to a custom cell library.
Verilog
10
star
27

cisco-vwic3-2mft

9
star
28

vga_i2c

VGA I2C GPIO + Atari 2600 Joystick Extender
HTML
8
star
29

spdif_pmod

S/PDIF Output PMOD
Verilog
8
star
30

rv32soc

Verilog
8
star
31

multi_port_mem

Implementing multi-port memories in FPGAs
Scala
6
star
32

uart2jtag_uart

Small project to connect UART pins to JTAG UART
Verilog
6
star
33

jtag_gpios

Tutorial on how to integrate custom JTAG functionality into existing tools
Verilog
6
star
34

dsp_guide

Jupyter Notebook
6
star
35

cpu_skeleton

Basic skeleton for an embedded Vexriscv CPU system.
Scala
5
star
36

usb_pmod

5
star
37

led_matrix

Scala
4
star
38

pixel_purse

2
star
39

galois

Python
2
star
40

bangbangbadge

2
star
41

arrow_deca_pmod_cape

2
star
42

yosys_split_ops

Yosys techmaps to split operations on large vectors into multiple smaller ones.
Verilog
2
star
43

ball

LED bal
G-code
2
star
44

arrow_deca_retro_cape

HTML
2
star
45

ocxo_workout

Python
1
star
46

spectroradiometer

C
1
star
47

max10_devkit_blinky

Tcl
1
star
48

icetap

FPGA Internal waveform capture tool
C
1
star
49

multi_video_streamer

HTML
1
star
50

tek420a

Random information about my Tektronix TDS 420A oscilloscope
Python
1
star
51

yosys_deconstructed

Verilog
1
star
52

yosys_techmap_blog

Example repo for blog post
Verilog
1
star
53

tang_primer_20k

GLSL
1
star
54

gps_interposer

C++
1
star
55

logic_analyzer

Verilog
1
star
56

kicad_personal

Personal library with KiCAD components
1
star
57

hp3478a_calibration

Script to dump HP 3478A calibration data over GPIB
Python
1
star
58

siglent_remote

Experiments to remote access my Siglent oscilloscope
C
1
star
59

formal_explorations

SystemVerilog
1
star
60

siglent_remote_blog

Collection of remote control scripts for Siglent oscilloscope
Python
1
star