Awesome AI for EDA

Table of Contents

• Surveys
• Papers
  • High Level Synthesis
  • Logic Synthesis
  • FloorPlanning & Placement
  • Routing
  • Testing and Verification
  • Machine Learning for SAT
  • Acceleration with Deep Learning Engine
  • Analog
• Other Resources

Survey

• Machine learning and pattern matching in physical design [pdf] [slide]
  • Bei Yu, David Z. Pan, Tetsuaki Matsunawa, Xuan Zeng. ASP-DAC 2015
• Accelerating chip design with machine learning: From pre-silicon to post-silicon
  • Cheng Zhuo, Bei Yu, Di Gao. SOCC 2017
• Machine Learning Applications in Physical Design : Recent Results and Directions [pdf] [slide]
  • Andrew B. Kahng. ISPD 2018
• Opportunities for Machine Learning in Electronic Design Automation
  • Peter Beerel, Massoud Pedram. ISCAS 2018
• Machine Learning and Systems for Building the Next Generation of EDA tools
  • Manish Pandey. ASP-DAC 2018
• New directions for learning-based IC design tools and methodologies [pdf]
  • Andrew B. Kahng. ASP-DAC 2018

Papers

High Level Synthesis

High-level synthesis (HLS) provides automatic conversion from C/C++/SystemC based specifications to hardware description languages (HDL). Particularly for HLS, ML has been adopted to produce fast and accurate result estimation, improve efficiency of Design Space Exploration (DSE) and assist DSE through an active-learning methodology.

• On learning-based methods for design-space exploration with high-level synthesis [pdf]
  • Hung-Yi Liu and Luca P. Carloni. DAC 2013
• Active learning for multi-objective optimization [pdf]
  • Marcela Zuluaga, Andreas Krause, Guillaume Sergent and Markus P¨uschel. ICML 2013
• Machine-learning based simulated annealer method for high level synthesis design space exploration [pdf]
  • Anushree Mahapatra and Benjamin Carrion Schafer. ESLsyn 2014
• Efficient and reliable high-level synthesis design space explorer for fpgas [pdf]
  • Dong Liu and Benjamin Carrion Schafer. FPL 2015
• Adaptive Threshold Non-Pareto Elimination: Re-thinking machine learning for system level design space exploration on FPGAs [pdf]
  • Pingfan Meng, Alric Althoff, Quentin Gautier, Ryan Kastner. DATE 2016
• Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine Learning [pdf]
  • Steve Dai, Yuan Zhou, Hang Zhang, Ecenur Ustun, Evangeline F.Y. Young, Zhiru Zhang. FCCM 2018
• Machine Learning for Design Space Exploration and Optimization of Manycore Systems [pdf]
  • Ryan Gary Kim, Janardhan Rao Doppa and Partha Pratim Pande. ICCAD'18
• HLSPredict: Cross Platform Performance Prediction for FPGA High-Level Synthesis [pdf]
  • Kenneth O’Neal, Mitch Liu, Hans Tang, Amin Kalantar, Kennen DeRenard, Philip Brisk. ICCAD 2018
• Pyramid: Machine Learning Framework to Estimate the Optimal Timing and Resource Usage of a High-Level Synthesis Design [pdf]
  • Hosein Mohammadi Makrani, Farnoud Farahmand, Hossein Sayadi, Sara Bondi, Sai Manoj Pudukotai Dinakarrao, Houman Homayoun, Setareh Rafatirad. FPL 2019
• XPPE: Cross-Platform Performance Estimation of Hardware Accelerators Using Machine Learning [pdf]
  • Hosein Mohammadi Makrani, Hossein Sayadi, Tinoosh Mohsenin, Setareh rafatirad, Avesta Sasan, Houman Homayoun. ASPDAC 2019
• A Deep-Reinforcement-Learning-Based Scheduler for FPGA HLS [pdf]
  • Hongzheng Chen and Minghua Shen. ICCAD 2019
• Machine Leaming to Set Meta-Heuristic Specific Parameters for High-Level Synthesis Design Space Exploration [pdf]
  • Zi Wang and Benjamin Carrion Schafer. DAC 2020
• Accurate Operation Delay Prediction for FPGA HLS Using Graph Neural Networks [pdf]
  • Ecenur Ustun, Chenhui Deng, Debjit Pal, Zhijing Li, and Zhiru Zhang. ICCAD 2020

Logic Synthesis

• Developing synthesis flows without human knowledge [pdf]
  • Cunxi Yu , Houping Xiao, Giovanni De Micheli. DAC 2018
• Deep Learning for Logic Optimization Algorithms [pdf]
  • Winston Haaswijk, Edo Collins, Benoit Seguin, Mathias Soeken, Frédéric Kaplan, Sabine Süsstrunk, Giovanni De Micheli. ISCAS 2018
• Accurate Wirelength Prediction for Placement-Aware Synthesis through Machine Learning [pdf]
  • Daijoon Hyun, Yuepeng Fan, Youngsoo Shin. DATE 2019
• Digital Compatible Synthesis, Placement and Implementation of Mixed-Signal Time-Domain Computing [pdf]
  • Zhengyu Chen, Hai Zhou, Jie Gu. DAC 2019
• LSOracle: a Logic Synthesis Framework Driven by AI
  • Walter Lau Neto, Max Austin, Scott Temple, Luca Amaru, Xifan Tang, Pierre-Emmanuel Gaillardon. ICCAD 2019
• DRiLLS: Deep Reinforcement Learning for Logic Synthesis [pdf]
  • Abdelrahman Hosny, Soheil Hashemi, Mohamed Shalan, Sherief Reda. ASP-DAC 2020

Power Network

• Template-based PDN Synthesis in Floorplan and Placement Using Classifier and CNN Techniques [pdf]
  • Vidya A. Chhabria, Andrew B. Kahng, Minsoo Kim, Uday Mallappa, Sachin S. Sapatnekar, Bangqi Xu. ASPDAC 2020

FloorPlanning & Placement

Based on the netlist after synthesis, FloorPlanning and Placement aim to assign the netlist components to specific locations on the chip layout. Better placement assignment implies potential of better chip area utilization, timing performance and routability. In order to achieve a better placement design for VLSI design, ML-based methods are recently applied to predict the possible challenges in further steps of physical design flow (e.g. routing steps).

prediction + search

• Chip Placement with Deep Reinforcement Learning [pdf] [blog]
  • Azalia Mirhoseini, Anna Goldie, et. al. ISPD 2020
• PADE: A High-Performance Placer with Automatic Datapath Extraction and Evaluation through High-Dimensional Data Learning [pdf]
  • Samuel Ward, Duo Ding, David Z. Pan. DAC 2012

prediction

• Evaluation of routability-driven macro placement with machine-learning technique [pdf]
  • Wei-Kai Cheng, Yu-Yin Guo, Chih-Shuan Wu. 2018 7th International Symposium on Next Generation Electronics (ISNE)
• Accurate Wirelength Prediction for Placement-Aware Synthesis through Machine Learning [pdf]
  • Daijoon Hyun, Yuepeng Fan, Youngsoo Shin. DATE 2019
• Template-based PDN Synthesis in Floorplan and Placement Using Classifier and CNN Techniques [pdf]
  • Vidya A. Chhabria, Andrew B. Kahng, Minsoo Kim, Uday Mallappa, Sachin S. Sapatnekar, Bangqi Xu. ASPDAC 2020
• Learning-Based Prediction of Embedded Memory Timing Failures During Initial Floorplan Design [pdf]
  • Wei-Ting J. Chan, Kun Young Chung, Andrew B. Kahng, Nancy D. MacDonald, Siddhartha Nath. ASPDAC 2016
• Device Placement Optimization with Reinforcement Learning [pdf]
  • Azalia Mirhoseini, Hieu Pham, Quoc V. Le et al. ICML 2017

MISC

• Placement and routing for 3D-FPGAs using reinforcement learning and support vector machines [pdf]
  • R. Manimegalai, E. Siva Soumya, V. Muralidharan, B. Ravindran, V. Kamakoti, D. Bhatia. VLSID 2005

Routing

Routing is one of the essential steps in VLSI physical design flow based on the placement assignment. Routing steps assign the wires to connect the netlist components on the chip. At the same time, routing steps need to satisfy the requirements of timing performance and total wire length without violating the DRC rules. The machine learning approaches are considered as powerful tools for congestion and timing prediction in detailed routing.

• Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine Learning [pdf]
  • Wei-Ting J. Chan, Pei-Hsin Ho, Andrew B. Kahng and Prashant Saxena3. ISPD 2017
• Accurate Machine-Learning-Based On-Chip Router Modeling [pdf]
  • Kwangok Jeong, Andrew B. Kahng, Bill Lin, Kambiz Samadi. IEEE Embedded Systems Letters (Volume: 2 , Issue: 3 , Sept. 2010)
• Placement and routing for 3D-FPGAs using reinforcement learning and support vector machines [pdf]
  • R. Manimegalai, E. Siva Soumya, V. Muralidharan, B. Ravindran, V. Kamakoti, D. Bhatia. VLSID 2005
• AENEID: A Generic Lithography-Friendly Detailed Router Based on Post-RET Data Learning and Hotspot Detection [pdf]
  • Duo Ding, Jhih-Rong Gao, Kun Yuan and David Z. Pan. DAC 2011
• Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis [pdf]
  • Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang. DATE 2019
• RouteNet: Routability prediction for Mixed-Size Designs Using Convolutional Neural Network [pdf]
  • Zhiyao Xie, Yu-Hung Huang, Guan-Qi Fang, Haoxing Ren, Shao-Yun Fang, Yiran Chen, Jiang Hu. ICCAD 2018
• High-Definition Routing Congestion Prediction for Large-Scale FPGAs [pdf]
  • Mohamed Baker Alawieh, Wuxi Li, Yibo Lin, Love Singhal, Mahesh A. Iyer, David Z. Pan. ASPDAC 2020
• Machine Learning-Based Pre-Routing Timing Prediction with Reduced Pessimism [pdf]
  • Erick Carvajal Barboza, Nishchal Shukla, Yiran Chen, Jiang Hu. DAC 2019
• Novel Congestion-estimation and Routability-prediction Methods based on Machine Learning for Modern FPGAs [pdf]
  • Abeer Al-Hyari, Ziad Abuowaimer, Timothy Martin, Gary William Gréwal, Shawki Areibi, Anthony Vannelli. ACM Transactions on Reconfigurable Technology and Systems, August 2019

Testing and Verification

Testing and verification is one of the most important process in chip design. However, with the diversity of applications and the complexity of design, traditional formal/specification testing can no longer meet the demands of various industries. Recently, more and more ML algorithms are used in test and verification process. The papers in this section aim at applying machine learning methods to solve testing and verification problems, making fast analog/RF system testing, building simplified estimation model, inferring and predicting the test results, optimizing sample strategies and even generating high quality test benches.

• Error moderation in low-cost machine-learning-based analog/RF testing [pdf]
  • Stratigopoulos, Haralampos-G., and Yiorgos Makris. IEEE TCAD of integrated CAS 2008
• HFMV: hybridizing formal methods and machine learning for verification of analog and mixed-signal circuits [pdf]
  • Hu, Hanbin, et al. DAC 2018
• High performance graph convolutional networks with applications in testability analysis [pdf]
  • Ma, Yuzhe, et al. DAC 2019
• RF specification test compaction using learning machines [pdf]
  • Stratigopoulos, Haralampos-G., et al. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2010
• Exploring Graphical Models with Bayesian Learning and MCMC for Failure Diagnosis [pdf]
  • Hongfei Wang, Wenjie Cai, Jianwen Li, and Kun He. ASPDAC 2020
• Learning to produce direct tests for security verification using constrained process discovery [pdf]
  • Kuo-Kai Hsieh, L. Wang, Wen Chen and J. Bhadra. DAC 2017
• Improving Test Chip Design Efficiency via Machine Learning [pdf]
  • Z. Liu, Q. Huang, C. Fang and R. D. Blanton. ITC 2019
• Machine learning for performance and power modeling of heterogeneous systems [pdf]
  • Greathouse, Joseph L., and Gabriel H. Loh. ICCAD 2018
• Low-cost high-accuracy variation characterization for nanoscale IC technologies via novel learning-based techniques [pdf]
  • Z. Pan et al. DATE 2018
• Learning-based approximation of interconnect delay and slew in signoff timing tools [pdf]
  • A. B. Kahng, S. Kang, H. Lee, S. Nath and J. Wadhwani. SLIP 2013
• LithoGAN: End-to-End Lithography Modeling with Generative Adversarial Networks [pdf]
  • W. Ye, M. B. Alawieh, Y. Lin and D. Z. Pan. DAC 2019
• Machine-Learning Based Congestion Estimation for Modern FPGAs [pdf]
  • D. Maarouf et al. FPL 2018
• System-level hardware failure prediction using deep learning [pdf]
  • X. Sun et al. DAC 2019

Machine learning for SAT Solver

SAT plays an important role in circuit design and verification, error diagnosis, model detection of finite state machines, FPGA routing, logic synthesis and mapping, register allocation, timing, etc. At the heart of a traditional SAT solver is a search engine that may require exponential runtime. Lately, with the advancement of neural network in representation learning and solving optimization problems, there have seen an increased interest in generating and solving SAT formula with neural network.

• Learning a SAT solver from single-bit supervision [pdf]
  • Daniel Selsam, Matthew Lamm, Benedikt Bünz, Percy Liang, Leonardo de Moura, and David L. Dill. ICLR 2019
• Guiding high-performance SAT solvers with unsat-core predictions [pdf]
  • Daniel Selsam and Nikolaj Bjørner. Theory and Applications of Satisfiability Testing – SAT 2019
• Learning Local Search Heuristics for Boolean Satisfiability [pdf]
  • Emre Yolcu and Barnabás Póczos. NeurIPS 2019
• G2SAT: Learning to Generate SAT Formulas [pdf]
  • Jiaxuan You, Haoze Wu, Clark Barrett, Raghuram Ramanujan and Jure Leskovec. NeurIPS 2019
• Learning to solve Circuit-SAT: An unsupervised differentiable approach [pdf]
  • Saeed Amizadeh, Sergiy Matusevych, and Markus Weimer. ICLR 2019

Acceleration with Deep Learning Engine

• DREAMPlace: Deep learning toolkit-enabled GPU acceleration for modern VLSI placement [pdf]
  • Yibo Lin, Shounak Dhar, Wuxi Li, Haoxing Ren, Brucek Khailany, David Z. Pan. DAC 2019

Analog

In the analog design flow, the topology of circuit is firstly determined for certain applications. Then the size of devices in selected topology are optimized to meet the exact specifications like DC gain or GBW. Recently, machine learning techniques are introduced to solve the device sizing and topology selection problems automatically.

Circuit Design

• Circuit-GNN: Graph Neural Networks for Distributed Circuit Design [pdf]
  • Guo Zhang, Hao He, DinaKatabi. ICML 2019
• Learning to Design Circuits [pdf]
  • Hanrui Wang, Jiacheng Yang, Hae-Seung Lee, Song Han. NIPS 2018
• AutoCkt: Deep Reinforcement Learning of Analog Circuit Designs [pdf]
  • Keertana Settaluri, Ameer Haj-Ali, Qijing Huang, Kourosh Hakhamaneshi, Borivoje Nikolic. DATE 2020
• BagNet: Berkeley Analog Generator with Layout Optimizer Boosted with Deep Neural Network [pdf]
  • Kourosh Hakhamaneshi, Nick Werblun, Pieter Abbeel, Vladimir Stojanovic. ICCAD 2019
• Late Break Result: An Efficient Learning-based Approach for Performance Exploration on Analog and RF Circuit Synthesis [pdf]
  • Hung-Ming Chen, Po-Cheng Pan, Chien-Chia Huang, Hung-Ming Chen. DAC 2019
• Application of Deep Learning in Analog Circuit Sizing [pdf]
  • Zhenyu Wang，Xiangzhong Luo，Zheng Gong. CSAI 2018
• Using Polynomial Regression and Artificial Neural Networks for Reusable Analog IC Sizing [pdf]
  • N. Lourenço, E. Afacan, R. Martins, F. Passos, A. Canelas, R. Póvoa, N. Horta, G. Dundar. SMACD 2019
• Machine-Learning-Based Early Stage Timing Prediction in SoC Physical Design [pdf]
  • Lida Bai, Lan Chen. ICSICT 2018
• Machine-Learning in Physical Design [pdf]
  • Bowen Li, Paul D. Franzon. EPEPS 2016
• Machine Learning Applications and Opportunities in IC Design Flow [pdf]
  • Laura Wang, Matt Luo. VLSI-DAT 2019

Topology Selection

• Electric analog circuit design with hypernetworks and a differential simulator [pdf]
  • Michael Rotman, Lior Wolf. ICASSP 2020
• Analog circuit topological feature extraction with unsupervised learning of new sub-structures [pdf]
  • Hao Li, Fanshu Jia, Alex Doboli. DATE 2016
• GA-SVM Optimization Kernel applied to Analog IC Design Automation [pdf]
  • Manuel Barros, Jorge Guilherme, Nuno Horta. ICECS 2006
• Using Artificial Neural Networks for Analog Integrated Circuit Design Automation [pdf]
  • N. Lourenço, et. al. Springer
• Inference of Suitable for Required Specification Analog Circuit Topology using Deep Learning [pdf]
  • Teruki Matsuba, Nobukazu Takai, Masafumi Fukuda, Yusuke Kubo. ISPACS 2018

Other resources

Collected by students in the course Computer-Aided Design of Digital Circuits and Systems (2020 Spring) of Tsinghua University (alphabetically ordered): Guyue Huang, Jingbo Hu, Yifan He, Jialong Liu, Mingyuan Ma, Chaoyang Shen, Juejian Wu, Yuanfan Xu, Hengrui Zhang, Kai Zhong

Instructor: Prof. Yu Wang          Teaching Assistant: Xuefei Ning

Any advice is appreciated, you can provide your suggestions by creating issues, or email [email protected].