syedarafia13/RISCV-RV32I-LOGISIM

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Rank 3,963,521 (Top 79 %)
Language Verilog
Created over 3 years ago
Updated over 3 years ago

syedarafia13/RISCV-RV32I-LOGISIM

syedarafia13

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RISCV is an open source software.

5-STAGE-PIPELINING-RV32I

system-verilog

RISCV-RV32I-CORE

verilog-practice

RISCV-CORE-FPGA

This repository contains RISCV (RV32I) Single Cycle Processor RTL design in SystemVerilog and Testbench in C++ for fpga.