syedarafia13/RISCV-CORE-FPGA syedarafia13/RISCV-CORE-FPGA

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  • Language SystemVerilog
  • Created over 2 years ago
  • Updated over 2 years ago
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syedarafia13/RISCV-CORE-FPGA
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syedarafia13

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Repository Details

This repository contains RISCV (RV32I) Single Cycle Processor RTL design in SystemVerilog and Testbench in C++ for fpga.

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