stnolting/riscv-debug-dtm

This repository has been archived on 06/Jan/2023
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Rank 1,084,038 (Top 22 %)
Language VHDL
License
BSD 3-Clause "New...
Created over 3 years ago
Updated almost 2 years ago

stnolting/riscv-debug-dtm

stnolting

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🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.

neorv32

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

neo430

💻 A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.

neoTRNG

🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).

fpga_puf

🔑 Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.

captouch

👇 Add capacitive touch buttons to any FPGA!

riscv-gcc-prebuilt

📦 Prebuilt RISC-V GCC toolchains for x64 Linux.

neorv32-verilog

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

fpga_torture

🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.

neorv32-riscof

✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.

cjtag_bridge

🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.

wb_spi_bridge

🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).

neorv32-formal

Formal verification (experiments) targeting the NEORV32 RISC-V processor.

msp430-gcc

Pre-compiled msp430-gcc compiler toolchains for 32/64-bit Windows and Linux machines.

74xx_discrete_clock

A retro-style digital clock based on 74xx discrete logic chips

neorv32-freertos

💾 FreeRTOS port for the NEORV32 RISC-V Processor.

neorv32-verif

✔️ Check the NEORV32 Processor for RISC-V compatibility.

neorv32-setups

Example setups for the NEORV32 RISC-V Processor

icarus-verilog-prebuilt

📦 Prebuilt Icarus Verilog simulator package for x64 Linux.