There are no reviews yet. Be the first to send feedback to the community and the maintainers!
sdram-controller
Verilog SDRAM memory controlleruart
Verilog uart receiver and transmitter modules for De0 Nanokicad-spice-demo
Demo of simulating kicad schematics in spicetls-examples
TLS access example code snippetsadc_interface
Verilog ADC interface for adc128s022 found in De0 Nanointelhex
Intel HEX file generatorac97
opencores ac97 controller verilog corewb_dma
Wishbone dma/bridge controller in verilyor1k-toolchain-build
OpenRISC toolchain build scriptsmor1kx-generic
mor1kx OpenRISC generic test harness support verilator and iverilogde0_nano-multicore
OpenRISC multicore SoC for De0 Nanoadc_preamp
Kicad schematic for opamp based microphone preamp circuit used with my adc_interface projectde0_nano
OpenRISC SOC for the De0 Nano FPGA dev boardstffrdhrn.github.io
Github blog for stafford hornefudosan
PHP, Twiiter Bootstrap, jQuery, CouchDB based webapp for managing real-estate property and client relationshipsor1k-utils
linux initramfs, testing, openocd, and other random utils for openrischostconfig
My backup of host and dot file configcgen
architecture code generation used by binutilsjunk
Dumping ground for test programs and ideas, mostly used for toolchain testingmicron-cores
FuseSOC cores for micron verilog modelsdigi-recorder
A digital recorder for fpga in verilog, tested on de0 nano.freemodelfoundry-cores
FuseSOC cores for free model foundry verilog modelsverilator_tb_utils
Verilator test bench utilsflipflop
Verilog flip flop project, basically hello world for De0 Nanobeeper
Verilog wave generator and pulse width modulator (PWM) for De0 Nanowiredelay
A wire delay simulation verilog coreberkeley-softfloat-2
Berkeley Softfloat 2c - with updatesegg_timer
Verilog egg timer for De0 Nanodram_tester
A testsuite for my dram controllerintgen
An verilog core for testing CPU interruptsLove Open Source and this site? Check out how you can help us