There are no reviews yet. Be the first to send feedback to the community and the maintainers!
VLSI
RISC V core implementation using Verilog.Standard-Cell-Characterization
Open Source tool to build liberty files and for Characterizing Standard Cells.Spider-Open-Source-Silicon-Foundation
Collection of installation and Tutorials on using open-source tools in VLSI domain. Baby steps in democratizing IC design and research for one and all.spy-rtos
Real time kernel for ARM-Cortex -M series processorsStandard-Cell-Library-skywater-130
Custom made Standard cell Library for skywater 130nm PDKspidey-suite
A module to add OTA Programming functionality to AVR MicrocontrollersACNN
🖼 Adaptive Convolutional Neural NetworksDark-Sight
🌙 Extreme Low-Light Image Processing Pipelineuav_ugv
Multi-agent assistive system : A cooperative surveillance system consisting UAV assisting an UGV.arboc
The aim of the project is to understand the dynamics of underwater robots in general and the effect of lift, drag and hydrodynamic coefficients on them and to simulate, validate and develop a snake-like robot which is robust enough to carry out underwater exploratory tasks.UHUGV
Unmanned Hybrid Underwater Ground Vehiclecerebro
The project proposes an approach towards EEG-driven position control of a robot arm by utilizing motor imagery, P300 waveform and Visually evoked Potential to align the robot arm with desired target position.spidey-sense
Contribution monitoring system.spider-tronix.github.io
Portfolio to showcase what we do. Also, a hobby project to practice web development for our members.Analog-MSM-Array
MultiStable Memory circuit designed based on LIQAF and integerated into dual port SRAM memory array design.Kin-Verification
A Deep Learning pipeline for the task of kin verification.Love Open Source and this site? Check out how you can help us