• Stars
    star
    67
  • Rank 461,056 (Top 10 %)
  • Language Verilog
  • License
    Apache License 2.0
  • Created about 4 years ago
  • Updated 12 months ago

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Repository Details

This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover