shinawy/RISC-V-Processor

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Updated over 3 years ago

shinawy/RISC-V-Processor

shinawy

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RISC-V processor on Nexys-A7 100T in verilog. Fully functional RISC-V architecture based pipelined processor using Verilog.

Tomasulu-Algorithm

Simulation Tomasulu algorithm for dynamic scheduling to support out-of-order execution