scale-lab/BLASYS

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26
Rank 912,933 (Top 19 %)
Language Verilog
License
BSD 3-Clause "New...
Created almost 5 years ago
Updated 8 months ago

scale-lab/BLASYS

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An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization

DRiLLS

DRiLLS: Deep Reinforcement Learning for Logic Synthesis Optimization (ASPDAC'20)

la-core

Linear algebra accelerators for RISC-V (published in ICCD 17)

OpenPhySyn

EDA physical synthesis optimization kit

DRUM

The Verilog source code for DRUM approximate multiplier.

PVTsensors

Designs for Process-Voltage-Temperature (PVT) Sensors with MCU

MTLoRA

The official implementation for MTLoRA: A Low-Rank Adaptation Approach for Efficient Multi-Task Learning

BACS

Benchmarks for Approximate Circuit Synthesis

ABACUS

ABACUS is a tool for approximate logic synthesis

FCNiris

A Resource-Efficient Embedded Iris Recognition System Using Fully Convolutional Networks

EDAonCloud

Characterizing and Optimizing EDA Flows for the Cloud (DATE'2021 and TCAD)

BitTrain

SEC'21: Sparse Bitmap Compression for Memory-Efficient Training onthe Edge

ARBench

Benchmark for Mobile Augmented Reality Applications

AdaMTL

AdaMTL: Adaptive Input-dependent Inference for Efficient Multi-Task Learning

MILPTune

Automatic MILP solver conﬁguration by learning problem similarities

ASPENN

Alternating-Blind-Identification

clusterSoCBench

A set of benchmarks to stress GPGPU accelerated cluster of ARM SoCs (tested with Nvidia TX1)

Jupyter Notebook

DPC

Decentralized Power Capping tool for a cluster of servers.