-
Stars3
-
Rank 3,856,041 (Top 79 %)
-
Language Makefile
-
License
Creative Commons ... -
Created 11 months ago
-
Updated 6 months ago
Reviews
There are no reviews yet. Be the first to send feedback to the community and the maintainers!
Repository Details
Cycle & Instret Privilege Mode Filtering Architecture Extension
More Repositories
1
riscv-isa-manual
RISC-V Instruction Set ManualTeX
3,320
2
riscv-v-spec
Working draft of the proposed RISC-V V vector extensionAssembly
873
3
riscv-opcodes
RISC-V OpcodesPython
597
4
riscv-debug-spec
Working Draft of the RISC-V Debug Specification StandardPython
430
5
sail-riscv
Sail RISC-V model
Coq
396
6
riscv-crypto
RISC-V cryptography extensions standardisation work.C
337
7
meta-riscv
OpenEmbedded/Yocto layer for RISC-V Architecture
BitBake
327
8
riscv-fast-interrupt
Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
216
9
riscv-bitmanip
Working draft of the proposed RISC-V Bitmanipulation extension
Makefile
205
10
learn
Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.
169
11
riscv-j-extension
Working Draft of the RISC-V J Extension Specification
Makefile
144
12
riscv-p-spec
RISC-V Packed SIMD Extension
131
13
riscv-plic-spec
PLIC Specification
119
14
riscv-platform-specs
RISC-V Profiles and Platform Specification
Makefile
110
15
riscv-profiles
RISC-V Architecture Profiles
Makefile
80
16
riscv-cfi
This repo holds the work area and revisions of the RISC-V CFI (Shadow Stack and Landing Pads) specifications. CFI defines the privileged and unprivileged ISA extensions that can be used by privileged and unprivileged programs to protect the integrity of their control-flow.
Makefile
74
17
docs-dev-guide
Documentation developer guideTeX
64
18
riscv-aia
58
19
riscv-test-env
C
38
20
configuration-structure
RISC-V Configuration StructurePython
35
21
riscv-aclint
Makefile
35
22
virtual-memory
34
23
riscv-bfloat16
Makefile
25
24
riscv-cheri
This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.Python
22
25
riscv-smmtt
This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant security use cases e.g. confidential-computing, trusted platform services, fault isolation and so on.
Makefile
20
26
docs-spec-template
Makefile
14
27
riscv-smbios
RISC-V SMBIOS Type 44 SpecTeX
13
28
docs-resources
12
29
riscv-spmp
The repo contains the SPMP architectural specification, which includes capabilities like access control of read/write/execute requests by an hart, address matching, encoding of permissions, exceptions for access violation, and support for virtualization.TeX
11
30
riscv-control-transfer-records
This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usages associated with profiling and debug.
Makefile
11
31
riscv-zacas
riscv-zacas created from docs-spec-template template
Makefile
9
32
riscv-zabha
The Zabha extension provides support for byte and halfword atomic memory operations.
Makefile
6
33
riscv-svadu
The Svadu extension adds support and CSR control for hardware updating of PTE A/D bits.
Makefile
6
34
riscv-attached-matrix-facility
Attached Matrix Facility Specification
Makefile
5
35
riscv-docs-base-container-image
A base container image populated with the dependencies to build the RISC-V Documentation.
5
36
riscv-b
"B" extension - that represents the collection of the Zba, Zbb, and Zbs extensions
Makefile
4
37
riscv-zaamo-zalrsc
Zaamo / Zalrsc: A extension components
Makefile
4
38
riscv-state-enable
TeX
3
39
riscv-software-ecosystem
A curated list of the status of different softwares on RISC-V
3
40
riscv-double-trap
RISC-V Double Trap Fast-Track Extension
Makefile
3
41
riscv-glossary
2
42
riscv-ssqosid
This repo will hold the specification for the proposed QoS ID extension being pursued on the fast-track process.
Makefile
2
43
riscv-indirect-csr-access
Smcsrind/Sscsrind is an ISA extension that extends the indirect CSR access mechanism originally defined as part of the Smaia/Ssaia extensions, in order to make it available for use by other extensions without creating an unnecessary dependence on Smaia/Ssaia.
Makefile
2
44
integrated-matrix-extension
Source code repository for the Integrated Matrix Facility Task Group
Makefile
2
45
.github
1
46
riscv-ssrastraps
The RAS exception and interrupts extension (Ssrastraps) defines standard local interrupt numbers and exception-cause codes for reporting errors detected by RAS functions in the system.TeX
1
47
riscv-zalasr
The ISA specification for the Zalasr extension.
Makefile
1
48
riscv-performance-events
RISC-V Performance Events Specification
Makefile
1
49
riscv-svvptc
Eliding Memory-management Fences on setting PTE valid (Svvptc)
Makefile
1
50
riscv-pqc
Post Quantum Cryptography
Makefile
1
51
riscv-ssdtso
The Ssdtso is a fast-track extension adding a 'dynamic-RVTSO' mode of operation and on-demand per-hart switching between the memory models.
Makefile
1
52
lightweight-isolation
The Lightweight Isolation Specification
Makefile
1
53
riscv-dot-product
Dot-Product Extension
Makefile
1
54
riscv-hac
High Assurance Cryptography
Makefile
1
55
riscv-smcdeleg-ssccfg
Supervisor Counter Delegation Architecture Extension
Makefile
1
56
riscv-zilsd
Zilsd (Load/Store Pair for RV32) Fast-Track Extension
Makefile
1
57
riscv-ras-eri
The (RAS Error-record Register Interface) RERI provides a specification to augment RAS features in RISC-V SOC hardware to standardize reporting and logging of errors by means of a memory-mapped register interface to enable error detection, provide the facility to log the detected errors (including their severity, nature, and location), and configuring means to report the error to a handler component.TeX
1