riscv-non-isa/rvv-intrinsic-doc

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riscv-non-isa/rvv-intrinsic-doc

riscv-non-isa

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RISC-V Vector Extension Intrinsic Document

Copyright and License Information

The RISC-V Vector Extension Intrinsic Document is

© 2021 Hsiangkai Wang [email protected]

© 2021 Zakk Chen [email protected]

© 2021 Kito Cheng [email protected]

© 2021 Yi-Hsiu, Hsu [email protected]

© 2021 Roger Ferrer Ibanez [email protected]

© 2021 Nick Knight [email protected]

© 2021 Mingjie Xing [email protected]

In general:

code is licensed under the BSD 3-clause license (SPDX license identifier BSD-3-Clause); while
documentation is licensed under the Creative Commons Attribution 4.0 International license (SPDX license identifier CC-BY-4.0).

The files COPYING.BSD and COPYING.CC in the top level directory contain the complete text of these licenses.

riscv-asm-manual

RISC-V Assembly Programmer's Manual

riscv-elf-psabi-doc

A RISC-V ELF psABI Document

riscv-arch-test

riscv-sbi-doc

Documentation for the RISC-V Supervisor Binary Interface

riscv-toolchain-conventions

Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains

riscv-trace-spec

RISC-V Processor Trace Specification

riscv-c-api-doc

Documentation of the RISC-V C API

riscv-iommu

Non-ISA IOMMU specification developed by the IOMMU TG.

riscv-device-tree-doc

RISC-V Specific Device Tree Documentation

riscv-ap-tee

This repo holds the work area and revisions of the RISC-V AP-TEEI specification. This specification defines the programming interfaces (ABI) to support a scalable confidential compute architecture for RISC-V application-processor platforms.

tg-nexus-trace

RISC-V Nexus Trace TG documentation and reference code

riscv-semihosting

riscv-uefi

riscv-brs

The Boot and Runtime Services (BRS) specification provides the software requirements for system vendors and Operating System Vendors (OSVs) to interoperate with one another by providing expectations for the Operating System (OS) to utilize in acts of device discovery, system management, and other rich operations provided in this specification.

riscv-arch-test-reports

riscv-security-model

RISC-V Security Model

riscv-acpi

riscv-ap-tee-io

This TG will define AP-TEE-IO ABI extensions to provide Confidential VM-assigned devices with secure direct access to confidential memory as well as MMIO, removing the dependence on para-virtualized I/O.

riscv-rvm-csi

RVM-CSI (RISC-V eMbedded - Common Software Interface) aims to provide a source-level portability layer providing a simplified transition path between different microcontrollers based on RISC-V. This repo contains the specification documentation, and language-specific source files for implementing the API (initially, C header files).

riscv-swi

RISC-V Software Interrupts Specification

riscv-server-platform

The RISC-V Server Platform specification defines a standardized set of hardware and sofware capabilities, that portable system software, such as operating systems and hypervisors, can rely on being present in a RISC-V server platform.

riscv-acpi-ffh

The repo will be used to hold the draft non-ISA RISC-V ACPI Functional Fixed Hardware (FFH) specification

server-soc-ts

Test suite for Server SoC

e-trace-encap

E-Trace Encapsulation Specification

riscv-rpmi

RISC-V Platform Management Interface Specification. OS-agnostic messaging interface for system management and control

riscv-cbqri

This repo holds the work area and revisions of a QoS register interface for caches and memory controllers specification. The QoS register interface is a non-ISA specification that supports configuring resource allocations to applications and monitoring the resource usage by applications.

riscv-acpi-rimt

RISC-V ACPI I/O MMU Table Specification

server-soc

The repo holds the draft non-ISA Server SoC specification being developed by the Server SoC specification TG and to release intermediate releases of the specification on milestones. Further downstream this repo will be used to release specifications for public review.