Discover refaay/Pipelined-MIPS-Processor Open Source project

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Language Verilog
Created about 6 years ago
Updated almost 6 years ago

refaay

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Pipelined RISC Architecture MIPS Processor using Verilog. Full pipelined with forwarding, stalling, and branch control hazard unit (minor errors with race conditions and sw forwarding, no jump). Spring 17.

Adders-and-Array-Multiplier

The modules are: • n-bit Ripple Carry Adder (RCA) [parameter: n] • n-bit Carry Look-ahead Adder (CLA); n=2, 3, 4 [parameter: n] • n-bit Carry Select Adder [parameters: n (multiple of k), block size (k), and block type (CLA or RCA)] • nxm unsigned array multiplier [parameters: n and m; each should be a power of 2 number].

Verilog

Faster-R-CNN-resnet50-PASCAL-VOC-2007

This project implements a neural network that can best detect the 20 different object classes of the PASCAL VOC 2007 challenge using the Keras and Tensorflow frameworks on Python 2.7. It uses Faster R-CNN resnet50 model is loaded with pre-trained weights.

Python

MIPS-Pipelined-Processor-GUI-Simulator

R4000 Pipelined MIPS CPU in GUI using C++ & Qt in a team. Computer Architecture. Spring 17

C++

CMOS_Standard_Cell_Library

CMOS standard cell library (schematic and layout) using Electric VLSI and SPICE sim, Spring 18

AGS Script

refaay/Pipelined-MIPS-Processor

refaay

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