raja-aadhithan/System-Verilog

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Language Verilog
Created about 3 years ago
Updated over 2 years ago

raja-aadhithan/System-Verilog

raja-aadhithan

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Labs on System Verilog

Router-1x3-Design

Router with 3 FIFOs , synchronizer, FSM, and a register is built and verified using UVM. The router accepts data packets on a single 8-bit port and routes them to one of the three output channels - channel 0, channel 1 and channel 2.

Maven_silicon_Verilog

Verilog Programs used for advanced VLSI Design

LabView

Lab work on Signal Processing

Multisim

Nope! there is no code in this repository, just pure circuits.

B.Sc_Verilog

Basic Code of Verilog Programs, UG Level

Fedora

to sync terminal commands

MATLAB

Include mini projects and Lab works of M.Sc. program

UVM

UVM Drivers to Scoreboards... this repository has the codes split up and spilled up, assemble those and you get a RAM UVM test bench

M.Tech_Verilog

Files coded on projects and labs

Perl-Maven

Perl as a Scripting language for CAD tools

CheatSheet

VHDL

VHDL codes for small circuits as LAb work

Keil

assembly codes as lab work

HDLBits

https://hdlbits.01xz.net/

raja-aadhithan

Not sure when this repository gets saturated.

Python

Python as a Scripting language for CAD tools

RTL-design-for-MATLAB-model

Final semester project

LTSPICE

Circuit design based on MOSFETs