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Router-1x3-Design
Router with 3 FIFOs , synchronizer, FSM, and a register is built and verified using UVM. The router accepts data packets on a single 8-bit port and routes them to one of the three output channels - channel 0, channel 1 and channel 2.System-Verilog
Labs on System VerilogLabView
Lab work on Signal ProcessingMultisim
Nope! there is no code in this repository, just pure circuits.B.Sc_Verilog
Basic Code of Verilog Programs, UG LevelFedora
to sync terminal commandsMATLAB
Include mini projects and Lab works of M.Sc. programUVM
UVM Drivers to Scoreboards... this repository has the codes split up and spilled up, assemble those and you get a RAM UVM test benchM.Tech_Verilog
Files coded on projects and labsPerl-Maven
Perl as a Scripting language for CAD toolsCheatSheet
VHDL
VHDL codes for small circuits as LAb workKeil
assembly codes as lab workHDLBits
https://hdlbits.01xz.net/raja-aadhithan
Not sure when this repository gets saturated.Python
Python as a Scripting language for CAD toolsRTL-design-for-MATLAB-model
Final semester projectLTSPICE
Circuit design based on MOSFETsLove Open Source and this site? Check out how you can help us