Discover pulp-platform/redundancy_cells Open Source project

Stars
8
Rank 2,099,232 (Top 42 %)
Language SystemVerilog
License
Other
Created almost 4 years ago
Updated 3 months ago

pulp-platform

There are no reviews yet. Be the first to send feedback to the community and the maintainers!

SystemVerilog IPs and Modules for architectural redundancy designs.

axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

SystemVerilog

1,007

pulpino

An open-source microcontroller system based on RISC-V

876

pulp-dronet

A deep learning-powered visual navigation engine to enables autonomous navigation of pocket-size quadrotor - running on PULP

491

pulpissimo

This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

SystemVerilog

381

ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

365

pulp

This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.

SystemVerilog

343

common_cells

Common SystemVerilog components

SystemVerilog

331

mempool

A 256-RISC-V-core system with low-latency access into shared L1 memory.

273

bender

A dependency management tool for hardware projects.

Rust

232

snitch

⛔ DEPRECATED ⛔ Lean but mean RISC-V system!

SystemVerilog

218

cheshire

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

Verilog

194

riscv-dbg

RISC-V Debug Support for our PULP RISC-V Cores

SystemVerilog

183

FlooNoC

A Fast, Low-Overhead On-chip Network

SystemVerilog

131

pulp-sdk

hero

Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and an application-class host CPU, including full-stack software and hardware.

SystemVerilog

iDMA

A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)

SystemVerilog

pulp-nn

dory

A tool to deploy Deep Neural Networks on PULP-based SoC's

Python

carfield

A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.

Tcl

pulp-riscv-gnu-toolchain

spatz

Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.

register_interface

Generic Register Interface (contains various adapters)

SystemVerilog

pulp_soc

pulp_soc is the core building component of PULP based SoCs

SystemVerilog

morty

A SystemVerilog source file pickler.

Rust

snitch_cluster

An energy-efficient RISC-V floating-point compute cluster.

bigpulp

⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform

SystemVerilog

axi_riscv_atomics

AXI Adapter(s) for RISC-V Atomic Operations

SystemVerilog

nemo

NEural Minimizer for pytOrch

Python

common_verification

SystemVerilog modules and classes commonly used for verification

SystemVerilog

pulp-runtime

Simple runtime for Pulp platforms

redmule

SystemVerilog

pulp-dsp

quantlab

Shell

RVfplib

Optimized RISC-V FP emulation for 32-bit processors

Assembly

pulp_cluster

The multi-core cluster of a PULP system.

SystemVerilog

fann-on-mcu

svase

C++

culsans

Tightly-coupled cache coherence unit for CVA6 using the ACE protocol

pulp-trainlib

Floating-Point Optimized On-Device Learning Library for the PULP Platform.

tech_cells_generic

Technology dependent cells instantiated in the design for generic process (simulation, FPGA)

SystemVerilog

clint

RISC-V Core Local Interrupt Controller (CLINT)

SystemVerilog

cheshire-ihp130-o

Tcl

stream-ebpc

Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Lukas Cavigelli, Georg Rutishauser, Luca Benini.

SystemVerilog

axi_mem_if

Simple single-port AXI memory interface

SystemVerilog

uvm-components

Contains commonly used UVM components (agents, environments and tests).

SystemVerilog

hero-sdk

⛔ DEPRECATED ⛔ HERO Software Development Kit

Shell

ri5cy_gnu_toolchain

Makefile

jtag_dpi

JTAG DPI module for SystemVerilog RTL simulations

SystemVerilog

fpu

SystemVerilog

axi_llc

SystemVerilog

neureka

2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters

SystemVerilog

hyperbus

SystemVerilog

axi_spi_slave

SystemVerilog

quantlib

A library to train and deploy quantised Deep Neural Networks

Python

clic

RISC-V fast interrupt controller

SystemVerilog

axi_node

AXI X-Bar

SystemVerilog

serial_link

A simple, scalable, source-synchronous, all-digital DDR link

SystemVerilog

croc

A PULP SoC for education, easy to understand and extend with a full flow for a physical design.

SystemVerilog

banshee

Rust

occamy

A high-efficiency system-on-chip for floating-point compute workloads.

Python

rbe

Reconfigurable Binary Engine

SystemVerilog

sne

SystemVerilog

gvsoc

Pulp virtual platform

C++

axi_spi_master

SystemVerilog

hwpe-stream

IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system

SystemVerilog

Deeploy

ONNX-to-C Compiler for Heterogeneous SoCs

Python

fpu_div_sqrt_mvp

[UNRELEASED] FP div/sqrt unit for transprecision

SystemVerilog

ne16

Neural Engine, 16 input channels

SystemVerilog

trace_debugger

Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.

SystemVerilog

axi2apb

SystemVerilog

mibench

The MiBench testsuite, extended for use in general embedded environments

adv_dbg_if

Advanced Debug Interface

SystemVerilog

hci

Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores

SystemVerilog

trdb

RISC-V processor tracing tools and library

pulp-nn-mixed

pulp-freertos

FreeRTOS for PULP

ecg-tcn

Official code for ECG-TCN paper accepted for publication on AICAS2021

Python

safety_island

A reliable, real-time subsystem for the Carfield SoC

ELAU

SystemVerilog

jtag_pulp

Verilog

AI-deck-workshop

Assembly

pulp-debug-bridge

Tool to connect the workstation to the pulp targets abd interact with them

C++

hier-icache

SystemVerilog

quadrilatero

matrix-coprocessor for RISC-V

pulp-detector

chimera

Python

riscv-gnu-toolchain

GNU toolchain for PULP and RISC-V

gpio

Parametric GPIO Peripheral

SystemVerilog

cluster_interconnect

SystemVerilog

hwpe-mac-engine

An example Hardware Processing Engine

SystemVerilog

obi

OBI SystemVerilog synthesizable interconnect IPs for on-chip communication

SystemVerilog

ITA

SystemVerilog

pulp-rt-examples

fpu_ss

CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor

pulp-builder

apb_timer

pulp-transformer

pulp-ethernet

dram_rtl_sim

pulp-actions

pulp-platform/redundancy_cells

pulp-platform

Reviews

Repository Details

More Repositories