princeofpython/Computer-Architecture princeofpython/Computer-Architecture

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  • Language Verilog
  • Created about 5 years ago
  • Updated over 3 years ago
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princeofpython/Computer-Architecture
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Repository Details

Detailed and step by step implementation of RISC-V CPU from scratch using Verilog. This work is part of my academic course EE2003, Introduction to Computer Organisation in IIT Madras.

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