phamquanganhBKSET/risc_v phamquanganhBKSET/risc_v

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  • Language Verilog
  • Created over 2 years ago
  • Updated about 2 years ago
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phamquanganhBKSET/risc_v
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phamquanganhBKSET

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Repository Details

RISC-V 5 stages pipeline IF, ID, EX, MEM, WB with forwarding, stalling and branch prediction

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